About the position
As part of the team you will collaborate with ASIC design teams in the Central Hardware Group, peer Test and Product Engineers in Silicon Operations, and with Cisco Systems NPI teams. Collaborate with DFT, Reliability, Quality, Failure Analysis and Manufacturing teams to resolve silicon issues and support successful product ramp. This role will also provide test program updates views to Executive Management to communicate progress and highlight issues. You will be a Hardware Engineer in Silicon Operations focusing on the NPI Product engineering activities by bringing up ATE testing plan including defining test methodologies, coverage metrics, and corner conditions. You will support pattern generation/debugging, identify gaps in test coverage, characterize and release the test program to production. Apply sophisticated data analytics to optimize test efficiency and drive yield improvements. Collaborate with Design, SoC, DFT, Reliability, Quality, Failure Analysis and Manufacturing teams to resolve silicon issues and support successful product ramp.
Responsibilities
- Collaborate with ASIC design teams and peer Test and Product Engineers.
- Work with DFT, Reliability, Quality, Failure Analysis, and Manufacturing teams to resolve silicon issues.
- Provide test program updates to Executive Management.
- Define test methodologies, coverage metrics, and corner conditions for ATE testing.
- Support pattern generation and debugging.
- Identify gaps in test coverage and characterize test programs.
- Release test programs to production.
- Apply data analytics to optimize test efficiency and drive yield improvements.
Requirements
- Bachelor's degree (or higher) in Electrical Engineering/Computer Engineering (or equivalent experience).
- 8+ years' experience in SOC/VLSI/bring-up, production, characterization, and test engineering.
- Excellent working knowledge of Advantest 93000 tester for characterization and production testing.
- Proficiency in data analysis tools such as JMP, Python, and familiarity with statistical methods.
- Experience with yield improvement and test time reduction activities.
- Understanding of customer RMA including Failure analysis.
- Highly skilled in writing code in C, C++, Java, 93k test methods, Python.
Nice-to-haves
- Excellent knowledge of the latest state-of-the-art trends in DFT insertion techniques, including Scan, ATPG, JTAG and MBIST.
Benefits
- Quality medical, dental and vision insurance.
- 401(k) plan with a Cisco matching contribution.
- Short and long-term disability coverage.
- Basic life insurance.
- Numerous wellbeing offerings.
- Up to twelve paid holidays per calendar year.
- Floating holiday and a day off for birthday.
- Vacation time off policy with flexible limits.
- Sick time off policy with 80 hours provided on hire date.
- Paid time away for critical or emergency issues.
- Additional paid time to volunteer and give back to the community.
