R&D Intern - FPGA/RTL Design Engineer - 2026
About The Position
THE OPPORTUNITY The Intern – FPGA/RTL Design Engineer will report to the Research and Development (R&D) Director, Implementation. The successful individual in this role will learn and participate in the development of Silvus advanced research projects and will contribute to the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. These are exciting projects aimed at addressing challenging real-world communication needs. This internship is full-time, fully onsite, Monday through Friday, at Silvus Technologies’ HQ in the heart of vibrant West LA. The following is a list of at least some of the current essential job functions of this internship opportunity.
Requirements
- In-progress Bachelor's degree or preferably an in-progress graduate degree in Electrical Engineering, or a closely related technical field.
- Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
- Knowledge of RTL design fundamentals using Verilog/VHDL.
- Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
- Must be a U.S. Citizen due to clients under U.S. government contracts.
- All employment is contingent upon the successful clearance of a background check and drug testing.
Nice To Haves
- MATLAB coding experience.
- Understanding of digital signal processing.
- Understanding of digital/analog/RF circuits and PHY/MAC-layer concepts.
Responsibilities
- Working with system engineers and digital design architecting for wireless communication projects.
- RTL coding, simulation, and test bench development.
- FPGA synthesis and timing closure.
- Hardware verification and troubleshooting.
- Opportunities to further engage, learn, and develop skills as projects progress.
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What This Job Offers
Job Type
Full-time
Career Level
Intern
