ASIC Design Verification Engineer

QualcommSanta Clara, CA
1d

About The Position

Qualcomm-Atheros is a leading provider of wireless and wired technologies for the mobile, networking, computing and consumer electronics markets. We're focused on inventing technologies that connect and empower people in ways that are elegant and accessible to all. Qualcomm Atheros' teams deliver cutting-edge products across every established wireless standard/protocol. We are currently seeking candidates for positions involving the implementation of optimum system architectures, interfaces and logics for connectivity RF/Analog system. Successful candidates will be responsible for participating in development of leading-edge ASICs for multi-function mobile platforms. Candidates will work with engineers or develop unit-level and integrated-level test benches. Candidate will assist in synthesis and gate-level simulation tasks related to your module and will assist with timing of the entire chip. Candidate will leverage knowledge of wireless LAN, Bluetooth, and RF transceiver. Ideal candidate will have: RTL Design ASIC front-end experience Scripting Languages knowledge (e.g. Perl or Python)

Requirements

  • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field.

Nice To Haves

  • RTL Design
  • ASIC front-end experience
  • Scripting Languages knowledge (e.g. Perl or Python)
  • knowledge of wireless LAN, Bluetooth, and RF transceiver

Responsibilities

  • participating in development of leading-edge ASICs for multi-function mobile platforms
  • develop unit-level and integrated-level test benches
  • assist in synthesis and gate-level simulation tasks related to your module
  • assist with timing of the entire chip
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