ASIC & FPGA Design Engineer Sr

Lockheed Martin•Orlando, FL

1d•Hybrid

About The Position

You will be the Senior ASIC & FPGA Design Engineer for the Multi Domain Missile Warning Payload team. Our team creates large format, high frame rate imaging sensor systems that provide survivability enhancing situational awareness for air, space and surface platforms. What You Will Be Doing As the Senior ASIC & FPGA Design Engineer you will work side by side with a PLD subject matter expert to architect, design and implement programmable logic solutions for the imaging sensor system. You will integrate hardware, develop test plans and verify performance on demanding space based platforms, contributing to a scalable, high performance missile warning payload. Why Join Us Do you want to be part of a company culture that empowers employees to think big, lead with a growth mindset, and make the impossible a reality? We provide the resources and give you the flexibility to enable inspiration and focus. If you have the passion and courage to dream big, work hard, and have fun doing what you love then we want to build a better tomorrow with you. We offer flexible work schedules to comprehensive benefits investing in your future and security, Learn more about Lockheed Martin’s comprehensive benefits package here. Further Information About This Opportunity: This position is in Orlando. Discover more about our Orlando, Florida location. MUST BE A U.S. CITIZEN - This position is located at a facility that requires special access. The selected candidate must be able to obtain a secret clearance. A company-sponsored Interim Secret is required to start. Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics. The application window will close in 90 days; applicants are encouraged to apply within 5 - 30 days of the requisition posting date in order to receive optimal consideration. Join us at Lockheed Martin, where your mission is ours. Our customers tackle the hardest missions. Those that demand extraordinary amounts of courage, resilience and precision. They’re dangerous. Critical. Sometimes they even provide an opportunity to change the world and save lives. Those are the missions we care about. As a leading technology innovation company, Lockheed Martin’s vast team works with partners around the world to bring proven performance to our customers’ toughest challenges. Lockheed Martin has employees based in many states throughout the U.S., and Internationally, with business locations in many nations and territories. Other Important Information By applying to this job, you are expressing interest in this position and could be considered for other career opportunities where similar skills and requirements have been identified as a match. Should this match be identified you may be contacted for this and future openings.

Requirements

Bachelor’s degree or higher in Electrical or Computer Engineering.
Relevant experience with FPGA design and simulation verification.
Minimum 2 years with Xilinx/AMD Vitis and Vivado toolsets.
At least 2 years of hands‑on experience using the Xilinx/AMD UltraScale design methodology.
2+ years working with AXI, Ethernet, TCP/IP, and PCIe specifications.
2+ years developing embedded C/C++ applications using Xilinx/AMD Vitis.
Minimum 2 years using Xilinx/AMD Vitis HLS tools.
2+ years of coding in Verilog, SystemVerilog, or VHDL.
At least 2 years of practical laboratory debug experience.
2+ years operating high‑speed oscilloscopes, spectrum analyzers, and pulse generators.
Minimum 2 years using Xilinx/AMD Vivado for FPGA debugging.
4+ years of experience with Linux/UNIX, including writing shell scripts (BASH, csh), Perl, and/or Python.
Strong communications, collaboration, and presentation skills.
MUST BE A U.S. CITIZEN - This position is located at a facility that requires special access. The selected candidate must be able to obtain a secret clearance. A company-sponsored Interim Secret is required to start.

Nice To Haves

LM design experience.
Missile experience.
MSEE or MSCE would be a plus.
Experience with SystemVerilog, Verilog, C/C++, MATLAB/Simulink, and SystemVerilog languages; Synopsys Synplify, Synopsys VCS, NCSim, ChipScope tool sets desired.
Experience with Xilinx/AMD and MicroSemi/Microchip part families, internal FPGA fabric and IP.
FPGA design experience using the tools noted above.
Previous experience related to aerospace design techniques would be a plus.
Prior experience with Lockheed Martin MFC is a plus.
Experience implementing NSA algorithms (e.g., AES, counter mode, etc.).
Experience managing configuration control (GitLab preferred).
Experience with Vivado and Vitis FPGA toolsets.
Experience with UVM.
Experience with Simulink and HDL Coder.
Comfortable using digital oscilloscopes, spectrum analyzers, power meters, signal generators, and other test equipment.
Experience with troubleshooting and debugging at board level, including FPGA validation.
Experience in ASIC/FPGA life‑cycle (architecture, design, simulation, verification, validation, integration & test).

Responsibilities

Define architecture and design specifications for programmable logic components, develop and document RTL (VHDL/Verilog/SystemVerilog) gate level designs that meet performance, power, and reliability requirements.
Create synthesis, place and route, and timing closure strategies to ensure deterministic operation.
Generate comprehensive test plans, simulation models, and verification environments (UVM, SystemC, Python based test benches) to validate functional correctness and timing margins.
Work closely with systems, mechanical, and software teams to integrate ASIC/FPGA solutions into the missile warning payload, ensuring compliance with interface, mass, and volume constraints.
Contribute to the creation and maintenance of design documentation, configuration management files, and version controlled repositories (e.g., Git).