ASIC Verification Engineer

Hewlett Packard Enterprise • Sunnyvale, CA

1d • Hybrid

About The Position

HPE Networking is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At HPE networking Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build world-class routers and switches. Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips. As part of our fast-paced chip design group, you will become an expert in building/validating high-speed ASICs. We give you opportunities to work on complex blocks where you can challenge yourself and grow. Open communications, empowerment, innovation, teamwork, and customer success are the foundations of the team. Thus, you set your own limits for learning, achievements, and rewards.

Requirements

• Bachelor’s degree required, Master’s strongly desired in Electrical Engineering or Computer Science/Engineering with 3-4 years of experience.
• Strong analytical/ problem solving skills.
• Strong coding skills in Verilog/System Verilog through courses and projects
• Experience in constrained-random verification with methodologies such as UVM is a strong plus.
• Experience building test benches using SV/UVM is strongly desired.
• Knowledge of Computer Architecture/networking protocols and machine learning through graduate level courses or previous work is a plus but not required.
• Knowledge of Perl/Python/C/C++.
• Excellent written and verbal communications skills is good to have.

Responsibilities

• You will be exposed to the latest verification methodologies such as UVM and you will enable complex feature verification suites.
• You will start with a functional specification of a module and produce a detailed test plan to verify the module.
• You will write functional models for the module using System Verilog/C/C++ for architectural validation.
• You will build the module level test bench using System Verilog/UVM
• You will write tests according to the test plan and find bugs in the module.
• You will be responsible for making sure your module is fully functional.
• You will work closely with logic designers to resolve bugs, with SW engineers to assist in driver code development.
• You will use state of the art tools for doing formal verification, code coverage analysis, gate sims, and more.
• You will also get a chance to be part of full chip/sub-system and emulation testing – which gives you exposure to the entire functionality of the chip/system.
• You get to participate in ASIC validation in the lab if you are passionate about making the chip come alive.
• You will also get a chance work on your leadership skills by mentoring interns and new college graduates.

Benefits

• We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
• We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
• We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level