DDR PHY Timing Design Engineer

Qualcomm • San Diego, CA

14d

About The Position

QCT DDR PHY team develops high-speed/low-power DRAM memory interface for all Qualcomm chipsets in latest DDR technologies. This position requires involvement in static timing analysis (STA) and closure of DDR PHY interface and internal logic components operating on high speed conventional and source synchronous DDR clocking scheme.

Requirements

• 2+ years industry experience with static timing analysis (STA) and PrimeTime constraints development.
• Unix/Perl/TCL scripting (must be comfortable with writing scripts)
• Excellent communication skills and ability to work across multiple teams across global locations.
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.
• Bachelor's degree in Electrical Engineering required, Master's preferred

Nice To Haves

• Experience in DDR interface operation and off-chip timing considerations, including signal/power integrity (LPDDRx, DDRx, HBM).
• Good understanding of architecture, system, and integration aspects for DDR PHYs.
• Good understanding of design for yield and production challenges with DDR systems.

Responsibilities

• Focused analysis and ownership of specific DDR PHY architecture components for timing closure bottlenecks and convergence feasibility.
• Identification and analysis of timing bottlenecks and mitigation solutions.
• Guidance to front-end and physical teams on all aspects of timing considerations.
• Development and support of PrimeTime STA timing constraints.
• Development of scripted automation for efficient data processing.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees