Design Verification Engineer

Marvell TechnologySanta Clara, CA
1d

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Custom Cloud Solutions (CCS) is a key business unit within Marvell's Data Center Group (DCG), focused on delivering tailored solutions for AI and cloud data centers to enhance performance and efficiency. CCS group develops cutting-edge SOCs and processors in advanced process nodes for some of the largest companies in the world, focusing on the growing data center, enterprise, and wireless markets. As part of the CCS group at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers’ specifications whether they’re a major telecom organization or automotive company, etc. What You Can Expect Work on verification of Marvell's AI/ML, Network Processing, Compute, Memory Expander and Accelerated Compute SOCs and IPs

Requirements

  • Bachelor’s Degree in Electrical Engineering, Electronics, Computer Engineering, or related fields with 2+ years of experience OR Master’s Degree in Electrical Engineering, Electronics, Computer Engineering, or related fields
  • Experience with Verilog and SystemVerilog, preferably with UVM
  • Basic proficiency with C/C++
  • Experience with scripting languages, e.g., Python or Perl
  • Working knowledge of the Linux operating system
  • Diligent and detail oriented
  • Willing to accept and work with differing opinions
  • Able to learn on the fly and work in a fast-paced environment

Responsibilities

  • Develop verification test plan based on architecture and design specifications
  • Gain understanding of complex/random System Verilog/UVM verification environments
  • Write and execute test cases
  • Debug failures and resolve issues working with design and verification team members
  • Run periodic regressions, triage failures, and resolve issues
  • Conduct coverage analysis and address coverage gaps
  • Develop deeper knowledge of ASIC development process

Benefits

  • employee stock purchase plan with a 2-year look back
  • family support programs to help balance work and home life
  • robust mental health resources to prioritize emotional well-being
  • recognition and service awards to celebrate contributions and milestones
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