Engineer, Design Verification Engineering
About The Position
About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X) . Engineer, Design Verification Engineering Analog Devices is expanding our team that architects, designs, and verifies Foundational Security Solutions to internal and external customers. This is an excellent opportunity to be part of a growing team with visibility and access across the company’s Business Units developing a wide range of leading-edge IC solutions that require or benefit from Secure HW/FW/SW.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Typically 2–5 years of experience in digital or mixed‑signal design verification.
- Proficiency in SystemVerilog and familiarity with UVM methodology.
- Experience with RTL simulation, waveform debug, and EDA verification tools .
- Solid understanding of digital design fundamentals , including FSMs, clocking, resets, and basic CDC concepts.
- Strong analytical, debugging, and problem‑solving skills.
- Ability to communicate technical issues clearly and collaborate across disciplines.
Nice To Haves
- Experience verifying security‑related hardware , such as cryptographic accelerators (AES, SHA, RSA, ECC), secure controllers, or root‑of‑trust blocks.
- Familiarity with secure boot flows , key storage, authentication mechanisms, and access control concepts.
- Knowledge of common interfaces used in SoCs (APB, AHB).
- Knowledge of formal verification
- Ability to utilize AI Agents or copilot to solve complex problems.
- Scripting experience ( Python, Perl, or TCL ) for verification automation.
Responsibilities
- Develop and execute design verification plans based on product requirements and architecture specifications.
- Create, enhance, and maintain SystemVerilog / UVM‑based/ C verification environments for block‑level and subsystem‑level verification.
- Write and debug directed and constrained‑random tests, checkers, assertions, and functional coverage.
- Collaborate closely with design engineers to understand design intent, debug failures, and drive closure of functional and coverage gaps.
- Analyze simulation results, identify root causes of issues, and clearly document findings.
- Support regression testing, verification sign‑off, and release readiness.
- Contribute to methodology improvements, reusable VIP, and best practices within the DV team.
- Interface with post‑silicon validation and lab teams to correlate pre‑silicon results and support silicon bring‑up as needed.
Benefits
- This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.
- This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time , and other benefits.
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
