Formal Equivalence Checking Methodology Engineer

NVIDIA • Santa Clara, CA

9d • Hybrid

About The Position

NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and outstanding people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is encouraged to do their best work. Come join the team and see how you can make a lasting impact on the world! We are seeking an expert and skilled Formal Equivalence Checking Methodology Engineer to join our VLSI team. This team is responsible for developing, maintaining, and optimizing RTL verification methodologies - Logical Equivalence and RTL Lint, for our ground breaking VLSI designs. This role is crucial in ensuring the functional equivalence of our designs throughout the design cycle, from RTL to GDSII!

Requirements

• BS in Electrical, Computer Engineering or equivalent experience with 3+ years of CAD experience; MS preferred
• Be familiar with Verilog and ASIC design along with experience in commercial EDA tools
• Knowledge or experience with Equivalence checking (FEC or FEV) and RTL Linting flows
• Strong scripting skills in languages such as Python, or Perl
• Excellent problem-solving, debugging, and analytical skills.
• Ability to work in a team environment and collaborate efficiently with multi-functional teams.
• Strong communication and documentation skills.

Nice To Haves

• Experience in other ASIC methodologies such as RTL Lint or Logic Synthesis
• Experience with advanced formal verification techniques, such as sequential equivalence checking, X-verification, and low-power equivalence sign-off.
• Strong understanding of AI and machine learning concepts, frameworks, or applications.

Responsibilities

• Develop and maintain robust equivalence checking flows (FEC/FEV) for different stages of the VLSI design cycle, including RTL-to-RTL, RTL-to-Gate, and Gate-to-Gate equivalence checking.
• Collaborate with ASIC design teams to understand design requirements and constraints.
• Optimize flows and methodologies for performance, capacity, and debug capabilities, ensuring efficient and effective verification of sophisticated VLSI designs.
• Support and debug aborts/failing verification, including debug of constraint related problems, RTL coding styles, and solution space exploration with the EDA tools to address performance bottlenecks
• Provide training and support to IP teams on formal verification methodologies, tools, and standard processes.
• Stay up to date with the latest advancements in equivalence checking techniques, tools, and methodologies.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees