Hardware Tools Engineer

OpenAI • San Francisco, CA

1d

About The Position

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.
You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems.
You’ll collaborate closely with architects, RTL designers, and verification engineers to translate real engineering friction into durable, scalable tooling solutions.

Requirements

• Demonstrated ability to build and maintain software (projects, internships, research, open source, or equivalent experience).
• Strong CS fundamentals: data structures, algorithms, debugging, and software design.
• Proficiency in at least one of Rust, C++, or Python (and willingness to learn the rest).
• Familiarity with digital design concepts and the ability to read RTL (Verilog/SystemVerilog) or equivalent hardware descriptions.
• Familiarity with compiler or IR-based ideas (representations, passes, transformations, lowering), through coursework or projects.
• Comfort operating in ambiguity and iterating quickly with users of your tools.

Nice To Haves

• Exposure to compiler and hardware toolchains such as XLS/DSLX, LLVM, Chisel/FIRRTL, CIRCT/MLIR, other novel hardware languages (e.g. HardCaml, SpinalHDL, Spade, PyMTL, Clash, BlueSpec, PyRope)
• Experience with Verilog tooling ecosystems (Yosys/RTLIL, Verilator, Slang) or writing tooling around them.
• Experience with build and test infrastructure (Bazel, CI systems, fuzzing, performance testing).
• Prior work touching synthesis, place and route, static timing analysis, or other PPA-related workflows.

Responsibilities

• Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation.
• Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows.
• Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure.
• Work closely with designers and verification engineers to turn real pain points into durable tools.
• Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability.
• Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts.
• Help enable PPA optimization loops by building analysis and automation around area, timing, and power tradeoffs, and by improving tooling that impacts those outcomes.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level
• Education Level: No Education Listed