High Performance Computing (HPC) Engineer

Cadence Systems•San Jose, CA

12h•Onsite

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are seeking a highly skilled HPC Engineer to join our team. The HPC Engineer is responsible for designing, implementing, and maintaining high‑performance software used for transistor‑level electrical circuit simulation in large‑scale, parallel computing environments. The ideal candidate has strong expertise in GPU-accelerated computation, distributed programming, and modern C++ development, along with a passion for solving complex problems, performance optimization and scalable numerical simulation. Position Location This is a full-time, on-site position based in San Jose, CA. In-office attendance is required.

Requirements

MS/PhD in Computer Science, Electrical Engineering, Mechanical Engineering, Aerospace Engineering, Physics, or a related technical field.
Demonstrated experience contributing to large-scale numerical simulation projects (e.g., computational physics, fluid dynamics, finite‑element analysis, thermal analysis).
Strong software engineering fundamentals, including design, refactoring, debugging, and testing of high-performance applications.
GPU programming : Expertise with CUDA, HIP, or other GPU computing frameworks.
Distributed programming : Expertise with MPI or similar message‑passing systems.
Parallel / multi-threaded programming : Expertise with OpenMP, pthreads, or other concurrency frameworks.
Performance optimization : Skilled in kernel-level and system-level performance tuning using profilers and code analyzers (e.g., Nsight, VTune, perf).
Modern C++ : Expertise with C++14/17 or later, including templates, RAII, standard libraries, and modern language patterns.
Software quality practices : Experience with unit testing, CI/CD automation, and code review processes.
AI-assisted development workflows : Ability to integrate AI tools into engineering workflows to enhance productivity and code quality.

Nice To Haves

2-4 years of industry experience developing numerical simulation codes.
Familiarity with VLSI circuit simulation concepts and electrical circuit analysis.
Background in numerical analysis, particularly numerical linear algebra, sparse matrix techniques, or methods for solving ODEs/PDEs.
Experience using hardware-level debugging and profiling tools to analyze performance bottlenecks.

Responsibilities

Architect, develop, and maintain HPC software for large-scale circuit simulation in distributed and GPU-accelerated environments.
Implement parallel and multi-threaded algorithms optimized for performance, scalability, and reliability.
Apply performance engineering techniques using profilers, code analyzers, and hardware-level instrumentation to optimize computational kernels and system workflows.
Collaborate with cross-functional engineering teams in a geographically distributed environment to deliver production-quality simulation technologies.
Contribute to continuous integration, unit testing, and code quality processes using modern C++ paradigms and AI‑assisted development workflows.