IP Logic Design Engineer

Intel Corporation • Austin, TX

3d • Hybrid

About The Position

Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Who We Are As part of Intel's Data Center Engineering Group, we develop cutting-edge IPs that serve as foundational components for the next generation of server processors. We specialize in the design and development of complex IP blocks and subsystems, with a strong emphasis on IO architecture Who You Are Your responsibilities include but not limited to: Defines, documents and designs the microarchitecture of IP blocks and subsystems Owns the register transfer level (RTL) development for the IP block and implements the specification for logic components Ensures quality of design through clean design partitioning, clear microarchitectural documentation, reviewing RTL design and verification of features Applies various strategies, tools and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals Delivers microarchitecture specifications (MAS) document along with detailed clear block diagram, signal level description, clocking details, power and timing requirements to capture the implementation details and ensure correct interactions between blocks or Ips Reviews the verification plan and implementation to ensure design features are verified correctly and implements corrective measures for failing RTL tests to ensure correctness of features Supports SoC customers to ensure high quality integration and verification of the IP block Drives quality assurance compliance for smooth IP to SoC handoff Supports post-silicon activity to enable various features Good problem-solving ability Excellent technical leadership/teamwork/communication skills and a proven ability to work with dynamic schedules

Requirements

• Candidate should possess a Bachelor's Degree – OR - Master's Degree in Electrical, Electronics or Computer Engineering
• 5+ years of experience in IP design for SoC or ASIC products.
• Experience in chip design with familiarity of the entire development flow from definition to tape-out
• Experience in high-speed I/O protocols (e.g., PCIe, CXL, Ethernet, proprietary interconnects).
• Experience with protocol conversion and coherency management between different domains (I/O and memory/coherent fabrics).
• Ability to debug and resolve issues across multiple domains (I/O, coherency, ordering).
• Proficiency in designing and verifying complex interface signals, including clock and power domain crossing.
• Hands-on experience with RTL design, simulation, debugging, triaging, running synthesis and timing analysis.
• Good problem-solving ability
• Excellent technical leadership/teamwork/communication skills and a proven ability to work with dynamic schedules

Nice To Haves

• System simulation models and debugging RTL/tests
• Experience in High-speed serial link protocols/IPs (PCIe, UPI, CXL, IOMMU etc)
• Experience in Computer architecture and PCIe, UPI, CXL, IOMMU, Cache Coherency protocols.
• Experience in authoring Functional Specifications
• Strong skills in interpreting and contributing to technical specifications and Solid problem-solving and analytical skills.

Responsibilities

• Defines, documents and designs the microarchitecture of IP blocks and subsystems
• Owns the register transfer level (RTL) development for the IP block and implements the specification for logic components
• Ensures quality of design through clean design partitioning, clear microarchitectural documentation, reviewing RTL design and verification of features
• Applies various strategies, tools and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals
• Delivers microarchitecture specifications (MAS) document along with detailed clear block diagram, signal level description, clocking details, power and timing requirements to capture the implementation details and ensure correct interactions between blocks or Ips
• Reviews the verification plan and implementation to ensure design features are verified correctly and implements corrective measures for failing RTL tests to ensure correctness of features
• Supports SoC customers to ensure high quality integration and verification of the IP block
• Drives quality assurance compliance for smooth IP to SoC handoff
• Supports post-silicon activity to enable various features

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level