Lead Mixed-Signal SoC Architect

PowerLattice Technologies Inc•Vancouver, WA

3d•Hybrid

About The Position

We are seeking a highly experienced and visionary Mixed-Signal SoC architect to define and lead the digital architecture of next-generation power chiplet System-on-Chip (SoC) platforms built around embedded MCU subsystems. This role requires deep expertise in embedded processing, system-level tradeoffs, and robust safety and security architecture design across the full product lifecycle.

Requirements

BS or MS in engineering or related fields.
25+ years of experience in semiconductor or embedded systems design
Proven track record of architecting and delivering MCU-based SoCs to production
Deep expertise in: Embedded MCU architectures (ARM Cortex-M, RISC-V, or equivalent) Real-time systems design and deterministic processing Memory systems (SRAM, TCM, MPU-based protection) On-chip interconnects (AHB, AXI-lite, or similar)
Strong, hands-on experience in safety and security architecture, including: Functional safety standards Safety mechanisms (lockstep, ECC, BIST, watchdogs, fault injection) Hardware security (secure boot, root of trust, key management, cryptographic accelerators) System-level threat modeling and mitigation for embedded devices
Strong understanding of firmware, RTOS, and hardware/software interaction
Experience with system modeling and performance analysis tools
Excellent leadership, communication, and cross-functional collaboration skills

Nice To Haves

Experience in safety-critical or high-reliability domains
Familiarity with embedded software platforms
Knowledge of power delivery application
Experience with silicon bring-up, validation, and post-silicon debug

Responsibilities

Lead end-to-end digital architecture for complex mixed- signal SoCs centered on embedded MCU subsystems
Define system partitioning, interconnect architecture, memory hierarchy, and IP integration strategy
Drive performance, power, area (PPA), safety, and security tradeoffs at the system level
Architect MCU subsystems for efficient, scalable embedded processing
Evaluate and select MCU cores (e.g., ARM Cortex-M, RISC-V MCUs, or custom cores)
Define memory architecture
Design interrupt architecture, DMA subsystems, and peripheral integration strategies
Define end-to-end functional safety architecture (e.g., fault detection, diagnostics, redundancy where required)
Architect hardware root of trust, secure boot, secure debug, and lifecycle management
Define system isolation using firewalls, and access control mechanisms
Drive threat modeling, vulnerability analysis, and mitigation strategies
Design scalable and efficient interconnects (e.g., AHB, AXI, or lightweight NoC)
Integrate peripherals and external interfaces with appropriate protection and isolation
Ensure efficient and secure data movement across the system
Collaborate with firmware and system software teams to optimize architecture and programmability
Define boot architecture, firmware update mechanisms, and runtime protections
Ensure long-term software scalability and platform flexibility
Provide architectural guidance across RTL, verification, firmware, safety, and security teams
Mentor senior engineers and influence cross-functional technical decisions
Lead architecture, safety, and security reviews