Lead SOC Physical Design Engineer

Qualcomm • Santa Clara, CA

157d • $203,300 - $304,900

About The Position

A Lead SOC Physical Design Engineer plays a crucial role in the development and implementation of products at Qualcomm. This role requires strong knowledge and experience with physical design tools (like Cadence or Synopsys), semiconductor processes, timing closure, clock tree synthesis, power optimization, and physical verification methodologies. Additionally, communication skills and the ability to lead multi-geo PD team are essential for success in this role.

Requirements

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

Nice To Haves

• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
• 12+ years of ASIC Physical design, physical verification, validation, integration, or related work experience.
• 5+ years of experience with physical design tools.
• 5+ years of experience with scripting tools and programming languages.
• 5+ years of experience with physical design verification methods.
• 4+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).

Responsibilities

• Leading and executing the physical design process of complex semiconductor chips, ensuring adherence to design specifications and requirements.
• Leading and driving the creation of chip floorplans, considering various factors like functionality, power, performance, area, and routing congestion to optimize the layout.
• Ensuring that the chip meets timing requirements by optimizing clock tree synthesis, placement, and routing.
• Leading and driving the placement and routing of logic gates and interconnects, optimizing for performance, power, and area.
• Implementing power-saving techniques and strategies to meet low-power design goals.
• Leading and guiding the conduction of design rule checks (DRC), layout versus schematic (LVS) checks, ERC and other miscellaneous checks to ensure the physical design meets manufacturing requirements.
• Ensuring that the chip meets the strict constraints of IR drop, Electromigration, and ESD path resistance checks.
• Working closely with design teams, CAD engineers, program management, IT and other cross-functional teams to achieve project goals and resolve design challenges.
• Leading the development and improvement of physical design and verification methodologies (including AI based), flows, and tools to enhance efficiency and quality of chip designs.
• Providing technical expertise, leadership and support within the physical design team across multi-geos. Also mentoring and guiding junior PD engineers.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants.
• Highly competitive benefits package designed to support success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Master's degree