Package Design Engineer, Silicon

Google • Mountain View, CA

1d

About The Position

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Requirements

• Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience.
• 2 years of experience in chip package substrate design using cadence APD (Allegro Package Designer) or mentor expedition.
• Experience in chip package substrate layout, design rules/verification, DFM and taping out for production.
• Experience in mobile SOC package design in the following technologies: FCCSP, Package on Package (PoP), InFO, RDL, IPD, 2.5D/3D, Chiplet.

Nice To Haves

• Experience in package outline, package routing strategy, bump and Ball Grid Array (BGA) definition and assignment.
• Experience designing for new packaging technologies and new silicon interfaces/subsystems.
• Experience in physical verification flow (e.g., LVS, DRC, connectivity).
• Experience with CAD for creating simple mechanical drawings, such as Package Outline Drawings (POD).
• Understanding of electromagnetic fundamentals for package design optimization.

Responsibilities

• Execute physical package substrate design of mobile SOC packages as an individual contributor, meeting performance/power/area requirements.
• Perform Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification of package designs.
• Participate in the development of new silicon IPs and packaging technology through feasibility studies and package test vehicle designs.
• Collaborate closely with Signal Integrity (SI)/Power Integrity (PI), Test, NPI and Mechanical Engineering teams to refine and optimize product package architecture and design.
• Interface with packaging suppliers, ensuring package design and Bill of Materials (BOM) documentation meets requirements for high volume manufacturing.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level