PhD Intern- Computer Science

Pacific Northwest National Laboratory•Richland, WA

About The Position

At PNNL, our core capabilities are divided among major departments that we refer to as Directorates within the Lab, focused on a specific area of scientific research or other function, with its own leadership team and dedicated budget. Our Science & Technology directorates include National Security, Earth and Biological Sciences, Physical and Computational Sciences, and Energy and Environment. In addition, we have an Environmental Molecular Sciences Laboratory, a Department of Energy, Office of Science user facility housed on the PNNL campus. The Physical and Computational Sciences Directorate's (PCSD’s) strengths in experimental, computational, and theoretical chemistry and materials science, together with our advanced computing, applied mathematics and data science capabilities, are central to the discovery mission we embrace at PNNL. But our most important resource is our people—experts across the range of scientific disciplines who team together to take on the biggest scientific challenges of our time. The Advanced Computing, Mathematics, and Data Division (ACMDD) focuses on basic and applied computing research encompassing artificial intelligence, applied mathematics, computing technologies, and data and computational engineering. Our scientists and engineers apply end-to-end co-design principles to advance future energy-efficient computing systems and design the next generation of algorithms to analyze, model, understand, and control the behavior of complex systems in science, energy, and national security We are seeking a PhD intern to contribute to a research compiler for high-level synthesis (HLS) toolchains that translate high-level computational graphs (e.g., linear algebra and machine learning workloads) into hardware implementations. The project sits at the intersection of compiler construction, computer architecture, and hardware/software co-design, with the broader goal of enabling end-to-end compilation from high-level abstractions to silicon using open-source infrastructure. The intern will work on IR design, lowering pipelines, and hardware-aware optimizations using the MLIR framework. This is a hands-on research role focused on rapid prototyping and full-stack compiler development. The intern will work on compiler infrastructure for high-level synthesis (HLS) toolchains that translate high-level computational graphs (e.g., linear algebra and machine learning workloads) into hardware implementations. The role focuses on building end-to-end flows from high-level IRs to silicon using open-source toolchains, including IR design, lowering pipelines, and hardware-aware optimizations using the MLIR compiler framework. This is a hands-on research role involving rapid prototyping and full-stack compiler development. The intern is also expected to contribute to research publications arising from this work.

Requirements

Candidates must be currently enrolled/matriculated in a PhD program at an accredited college.
Minimum GPA of 3.0 is required.

Nice To Haves

PhD student in Computer Science, Computer Engineering, Electrical Engineering, or related field.
Strong background in compilers or programming languages (IRs, transformations, SSA).
Interest in hardware/software co-design or accelerator compilation.
Coursework or experience in computer architecture and compiler design.
Familiarity with high-level synthesis or hardware compilation flows.
Strong C++ programming skills.
Experience working with research codebases and prototyping quickly.
Familiarity with MLIR or LLVM (strongly recommended).
Familiarity with Hardware Description Languages (e.g. Verilog, VHDL).
Experience with linear algebra, machine learning systems, or tensor compilers.
Ability to collaborate across compiler, architecture, and hardware domains.
Strong communication and documentation skills for research environments.

Responsibilities

Contribute to a research compiler for high-level synthesis (HLS) toolchains that translate high-level computational graphs (e.g., linear algebra and machine learning workloads) into hardware implementations.
Work on IR design, lowering pipelines, and hardware-aware optimizations using the MLIR framework.
Building end-to-end flows from high-level IRs to silicon using open-source toolchains
Contribute to research publications arising from this work.