Principal Analog Design Engineer

Chelsea Search Group • Los Angeles, CA

1d • Hybrid

About The Position

Principal Analog Design Engineer Location : Irvine, CA (preferred) or remote + travel to Irvine Responsibilities : Clock generation and distribution (VCOs, PLL, clock distribution, etc) Design of custom passive components, from concept to silicon implementation Fundamental analog blocks (bandgap references, LDOs, temp sensors, etc) High-speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.). New techniques for the development of next generation optical transceiver Silicon bring-up, debug and support Supervise analog layouts within advanced process nodes System verification and circuit design spec creation Team communication and documentation Requirements: Master’s degree and/or PhD (preferred) in Electrical Engineering or related fields with 5+ years of experience. Experience in advance cmos design and verification flows (tools to evaluate self-heating, electromigration, safe operating area) Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must Knowledge of the fundamentals on electromagnetism, lump models and high-frequency design Production level tape out experience Experience with TSMC FinFET process nodes (16nm/12nm, 7nm/N7, 5nm/N5, 3nm/N3, 2nm/N2) and optimization for high-performance circuits. Should have strong analog design fundamentals and experience in designing analog circuit blocks for broadband amplification, clock generation and distribution, and/or fundamental analog blocks. Strong communication and documentation skills Experience with electromagnetic simulation tools (EMX, Momentum, HFSS or other) is a plus Experienced in lab chip bring-up and debugging efforts is a plus Good understanding of analog layouts in FinFET and its effect on high-speed designs is a plus

Requirements

• Master’s degree and/or PhD (preferred) in Electrical Engineering or related fields with 5+ years of experience.
• Experience in advance cmos design and verification flows (tools to evaluate self-heating, electromigration, safe operating area)
• Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must
• Knowledge of the fundamentals on electromagnetism, lump models and high-frequency design
• Production level tape out experience
• Experience with TSMC FinFET process nodes (16nm/12nm, 7nm/N7, 5nm/N5, 3nm/N3, 2nm/N2) and optimization for high-performance circuits.
• Should have strong analog design fundamentals and experience in designing analog circuit blocks for broadband amplification, clock generation and distribution, and/or fundamental analog blocks.
• Strong communication and documentation skills

Nice To Haves

• Experience with electromagnetic simulation tools (EMX, Momentum, HFSS or other) is a plus
• Experienced in lab chip bring-up and debugging efforts is a plus
• Good understanding of analog layouts in FinFET and its effect on high-speed designs is a plus

Responsibilities

• Clock generation and distribution (VCOs, PLL, clock distribution, etc)
• Design of custom passive components, from concept to silicon implementation
• Fundamental analog blocks (bandgap references, LDOs, temp sensors, etc)
• High-speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.).
• New techniques for the development of next generation optical transceiver
• Silicon bring-up, debug and support
• Supervise analog layouts within advanced process nodes
• System verification and circuit design spec creation
• Team communication and documentation

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level