Principal Engineer, Verification
About The Position
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As part of the Design Verification Team at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers’ specifications whether they’re a major telecom organization or automotive company, etc. What You Can Expect Architect and implement simulation test bench in UVM. Develop and execute test-plans for verifying correctness and performance of the design. Own and debug failures in simulation to root-cause problems Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations Coach and mentor junior engineers of the team when necessary to achieve successful project outcomes.
Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 7+ years of related professional experience. Or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 4+ years of experience.
- Strong background in SOC verification and test bench development using UVM, System Verilog, C/C++, and DPI.
- Strong verification skills, understanding of methodology (object-oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations, data structure).
- Must have effective interpersonal and teamwork skills.
- Participate in problem solving and quality improvement activities.
- Demonstrate initiative and a bias for thoughtful action.
- Grounded, detail-oriented, always backs up ideas with facts.
- Must have the ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.
Responsibilities
- Architect and implement simulation test bench in UVM.
- Develop and execute test-plans for verifying correctness and performance of the design.
- Own and debug failures in simulation to root-cause problems
- Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations
- Coach and mentor junior engineers of the team when necessary to achieve successful project outcomes.
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs to help balance work and home life
- robust mental health resources to prioritize emotional well-being
- recognition and service awards to celebrate contributions and milestones
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What This Job Offers
Job Type
Full-time
Career Level
Principal
