Process Development Engineering Intern

Skywater•Kissimmee, FL

23h

About The Position

Our Internship program offers students an opportunity to receive training in a hi-tech environment. Throughout your internship, you will gain on-the-job process development experience while working alongside experienced professionals who provide you with both guidance and autonomy as you work on challenging projects. Our internship programs run typically May - August each year. Projects and responsibilities: Support the efforts of Process Development Module Engineers to prepare for and execute new semiconductor packaging processes. The following project descriptions are meant to capture the flavor of the projects that the interns will work on. Individual project assignments may vary from the descriptions provided below, depending on the immediate business needs. Project 1: Backgrind and Dicing Project Summary: The Dicing Intern will work with the process engineers to characterize process sensitivity of Kerf width as a function of process parameters such as saw blade thickness, Grit size, bond hardness, spindle rpm, feed rate and coolant pressure/ flow parameters. Key Objectives: Run experiments and generate Kerf maps of common substrates and thicknesses. Interpret CAD drawings from the customer and develop a methodology to set up dicing automation accordingly. Controlled test cuts will be performed on common substrate materials and thicknesses. Kerf will be measured precisely using standard methods and Kerf maps will be generated. The intern will also assist the dicing engineer in interpreting CAD files and setting up the Dicing tool automation accordingly. Project 2: Backgrind Process Characterization Project Summary: The Backgrind process intern will focus on understanding and controlling the variables that affect the grind process CTQs, namely final thickness, surface quality, grind stress, yield and throughput. Key Objectives: Understand the impact of key process input variables, and achieve tight thickness uniformity, control warpage, and prevent subsurface damage and cracks. Optimize throughput and quality during the backgrind and top grind process. Develop familiarity with consumable toolsets and process metrology tools such as Keyence microscopes. Evaluate the effect of process input variables such as: Device side topography, pre-grind warpage, grinding abrasive grit, bond type, dressing condition, dressing tape type, feed rate, downforce, coolant flow rate, on final thickness, TTV, WIWNU, mechanical grinding stresses, chipping, delamination, microcracking, post-grind warpage, and die cracking. Project 3: High-temp TBDB and hybrid bond process development Project Summary: This project involves developing a temporary bond and debond process (TBDB) that will allow for improved thermal budget during backside wafer thin film processing Key Objectives The Intern will work with the process engineer to help overcome process issues. Key challenges to overcome in the high temperature TBDB process is to balance high temperature survivability while minimizing post bond residue, controlling wafer bow, and preventing die cracking and edge chipping. Assist with optimizing surface preparation variables (wafer cleanliness, flatness, pretreatment, etc.), coating variables (spin curves, edge bead removal, film thickness range), cure variables (Bake Temperature, Time) and Bonding variables (Bond Temperature, Pressure, vacuum level, time, etc.) to optimize Bond strength, debond yield, control wafer bow, particle adders, residues, and electrical parameters. Project 4: Compression Molding Project Summary: The compression molding intern will work closely with the process engineers to develop robust compression molding processes for FOWLP. and troubleshoot voids, warpage, and delamination Key Objectives Assist the engineer in optimizing compression process variables (mold temperature, ramp rate, compression force, ramp, pressure profiles, flow time, cure time), vacuum levels, and outgassing for a given mold compound and panel and package stack, mold tool and cavity. Control CTE mismatch between the substrate and the EMC to produce integrated die molds with excellent cosmetic and dimensional finish with minimal warpage, cracks, flashing, delamination and voids with acceptable throughput. Project 5: LDI / Lithography Project Summary: The Lithography intern will work closely with the process engineers to develop robust patterning processes on Dry Film Resist using Laser Direct Write Technology. In addition, the intern will also work with Nikon Steppers, Contact Mask Aligners, and Track systems to develop photoresist coat, expose, and develop processes for Packaging applications. Key Objectives Assist the Lithography engineering team in developing processes for patterning Dry Film Resists (using LDI). Assist the Lithography engineering team in developing processes for the development of conventional liquid resist spin, bake and develop processes. Resist stripping processes are also in the scope of the duties. As well as resist measurement metrology using ellipsometry. Assist with CD SEM and Overlay measurement characterization and process window optimization. Project 6: Electroplating Intern Project Summary: The Electroplating intern will work closely with the process engineer to develop robust electroplating processes for Copper, Nickel, SnAg and Gold, and electroless plating processes for very high aspect ratio fills. In addition, the intern will also work with various plating bath metrology tools such as titrators, XRF, SEM, EDS, Cyclic Voltammetry, Profilometry and sheet resistance testing to characterize the electroplated deposits. The intern may also help the engineer develop and maintain wet etch chemistries. Key Objectives Work closely with the plating engineer to analyze and maintain the plating baths. Assist the engineer in the development of robust electroplating processes with good uniformity, fill characteristics, and low-stress films. If the scope and time permit, the intern will also develop superconformal electroless plating processes for high aspect ratio via fills.

Requirements

Degree Program: Completion of Junior year+ in a bachelor's degree program in the areas of Chemistry, Chemical Engineering, Materials Engineering, Polymer Engineering.
US Citizenship Required

Nice To Haves

Hands-on experience in setting up and running clean room experiments

Responsibilities

Support the efforts of Process Development Module Engineers to prepare for and execute new semiconductor packaging processes.
Dicing Intern will work with the process engineers to characterize process sensitivity of Kerf width as a function of process parameters such as saw blade thickness, Grit size, bond hardness, spindle rpm, feed rate and coolant pressure/ flow parameters.
Run experiments and generate Kerf maps of common substrates and thicknesses.
Interpret CAD drawings from the customer and develop a methodology to set up dicing automation accordingly.
Controlled test cuts will be performed on common substrate materials and thicknesses.
Kerf will be measured precisely using standard methods and Kerf maps will be generated.
Assist the dicing engineer in interpreting CAD files and setting up the Dicing tool automation accordingly.
Backgrind process intern will focus on understanding and controlling the variables that affect the grind process CTQs, namely final thickness, surface quality, grind stress, yield and throughput.
Understand the impact of key process input variables, and achieve tight thickness uniformity, control warpage, and prevent subsurface damage and cracks.
Optimize throughput and quality during the backgrind and top grind process.
Develop familiarity with consumable toolsets and process metrology tools such as Keyence microscopes.
Evaluate the effect of process input variables such as: Device side topography, pre-grind warpage, grinding abrasive grit, bond type, dressing condition, dressing tape type, feed rate, downforce, coolant flow rate, on final thickness, TTV, WIWNU, mechanical grinding stresses, chipping, delamination, microcracking, post-grind warpage, and die cracking.
Intern will work with the process engineer to help overcome process issues.
Assist with optimizing surface preparation variables (wafer cleanliness, flatness, pretreatment, etc.), coating variables (spin curves, edge bead removal, film thickness range), cure variables (Bake Temperature, Time) and Bonding variables (Bond Temperature, Pressure, vacuum level, time, etc.) to optimize Bond strength, debond yield, control wafer bow, particle adders, residues, and electrical parameters.
The compression molding intern will work closely with the process engineers to develop robust compression molding processes for FOWLP. and troubleshoot voids, warpage, and delamination
Assist the engineer in optimizing compression process variables (mold temperature, ramp rate, compression force, ramp, pressure profiles, flow time, cure time), vacuum levels, and outgassing for a given mold compound and panel and package stack, mold tool and cavity.
Control CTE mismatch between the substrate and the EMC to produce integrated die molds with excellent cosmetic and dimensional finish with minimal warpage, cracks, flashing, delamination and voids with acceptable throughput.
The Lithography intern will work closely with the process engineers to develop robust patterning processes on Dry Film Resist using Laser Direct Write Technology.
Assist the Lithography engineering team in developing processes for patterning Dry Film Resists (using LDI).
Assist the Lithography engineering team in developing processes for the development of conventional liquid resist spin, bake and develop processes.
Assist with CD SEM and Overlay measurement characterization and process window optimization.
The Electroplating intern will work closely with the process engineer to develop robust electroplating processes for Copper, Nickel, SnAg and Gold, and electroless plating processes for very high aspect ratio fills.
Work closely with the plating engineer to analyze and maintain the plating baths.
Assist the engineer in the development of robust electroplating processes with good uniformity, fill characteristics, and low-stress films.
If the scope and time permit, the intern will also develop superconformal electroless plating processes for high aspect ratio via fills.