Programmable Logic Engineer

Viasat, Inc. • Carlsbad, CA

5d • Hybrid

About The Position

One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.

In this role you will help develop high speed signal processing algorithms and/or network protocols in FPGAs. The individual will be responsible for the full design phase starting from the requirements' phase to documentation, block diagrams, implementation of source code, simulation, place & route, testing in hardware, and integration.

Requirements

• Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
• 5-8 years FPGA design experience, including Xilinx Vivado
• Strong knowledge of System Verilog
• Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders
• Proven track record to design and implement FPGA modules using System Verilog with simulation and testbench development
• Work independently, take initiative, and take ownership of tasks and results
• Strong written and verbal communication skills, ability to work with a geographically distributed team

Nice To Haves

• Familiarity with Matlab
• Experience with GitHub
• Experience with developing code for legacy Viasat modem platforms
• Familiarity with DVB-S2x and DVB-RCS2 standards
• Understanding and knowledge of Satellite communication waveforms and standards

Responsibilities

• Collaborate with team members to jointly develop high-speed digital signal processing and waveform processing algorithms supporting satellite communications applications
• Develop testbenches and help maintain and update system level verification environment
• Synthesize Verilog and System Verilog for Xilinx/AMD FPGAs
• Develop timing constraints, analyze timing results, and implement design changes required to close timing
• Generate and collaborate on required design documents, development requirements, specifications and verification protocols
• Responsible for owning and driving technical issues to resolution
• Integrate and debugs design in the laboratory

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level