RTL & Co-design Engineer (junior)
About The Position
About the Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.
Nice To Haves
- Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.
- Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.
- Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.
- Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.
- Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.
- Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.
- Passion for building industry-leading massive-scale hardware systems.
Responsibilities
- Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems
- Contribute to architectural studies including performance modeling and feasibility analysis.
- Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.
- Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.
- Build and review performance and functional models to validate design intent.
- Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
Education Level
No Education Listed
Number of Employees
5,001-10,000 employees
