RTL Engineer, Power Macromodeling

Samsung Semiconductor•San Jose, CA

13d•Onsite

About The Position

We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models. Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy Reports to: SVP, R&D (Power & Thermal Lab)

Requirements

Bachelors degree 15+ years of experience or Masters degree 13+ years of experience.
Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC).
Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects.
Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc.
Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect.
Familiarity with SystemC or transaction-level modeling.
Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models.
Knowledge of power macromodeling, power estimation flows, or architectural power analysis.

Nice To Haves

Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O.
Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity.
Exposure to low-power design and thermal management.
Exposure to power macromodeling, power estimation flows, or architectural power analysis.

Responsibilities

Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid.
Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations.
Define power-relevant functional states (transaction/state-based abstraction).
Support trace-driven power modeling, aligned with C/SystemC workload traces.
Perform synthesis-assisted calibration using average and worst-case power anchors when available.
Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available.
Collaborate with software engineers on feature semantics, timing alignment, and model interfaces.
Contribute to scalable IP-wise composition for full-system power simulation.

Benefits

The pay range below is for all roles at this level across all US locations and functions.
Individual pay rates depend on a number of factors—including the role’s function and location, as well as the individual’s knowledge, skills, experience, education, and training.
We also offer incentive opportunities that reward employees based on individual and company performance.
This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones.
In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves.
An investment in your future is an investment in ours.
Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you’ll have support no matter where you are.
Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.
Embrace Flexibility Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.