Senior Design Verification Engineer

Qualcomm•San Diego, CA

About The Position

This individual independently plans, performs the moderately-defined responsibility for the development of test plans and the functional verification on hardware at the IP, sub-system, SoC and system/architecture level for wireless and wired technologies using an object-oriented verification language called SystemVerilog in an OVM or UVM verification environment. Performs Physical and/or Mac Layer verification in developing the methodology architectural components and verification infrastructure. Responsibilities include working with the Architects, ASIC designers and Software Engineers on SoCs for mobile handset and consumer electronic applications. Writes and implements feature-based test plans, debug test failures, run regression and close test plan targets. Acts as a strong contributor at design reviews and project meetings.

Requirements

Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field.
Bachelor's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field and five (5) years of progressive experience in a related occupation.
Employer will accept any suitable combination of education, training or experience.

Responsibilities

Plans and performs functional verification on hardware at various levels (IP, sub-system, SoC, system/architecture)
Develops test plans
Uses SystemVerilog in an OVM or UVM verification environment
Performs Physical and/or Mac Layer verification
Develops methodology architectural components and verification infrastructure
Works with Architects, ASIC designers, and Software Engineers
Writes and implements feature-based test plans
Debugs test failures
Runs regression and close test plan targets
Acts as a strong contributor at design reviews and project meetings