Senior Design Verification Engineer

Qualcomm • Santa Clara, CA

1d

About The Position

As a Senior Design Verification Engineer, you will contribute to ASIC verification efforts for IPs, subsystems, and SoCs used across Qualcomm’s Wi‑Fi, connectivity, and IoT platforms. You will collaborate closely with SoC architects, design, software, and validation teams to verify IPs that meet power, performance, and area goals. Additionally, you will help define and improve verification processes, methodologies, and tools for large, complex IPs and subsystems.

Requirements

• 3+ years of practical ASIC design verification experience, including ownership of verification for complex SoC subsystems or IP blocks
• Strong experience across digital design verification, including test automation, constrained‑random testing, code and functional coverage, SystemVerilog assertions (SVA), and performance verification
• Proven expertise in SystemVerilog and UVM‑based verification methodologies, including assertion-based and coverage-driven verification
• Strong analytical, debugging, and problem-solving skills, with the ability to lead complex technical investigations
• Experience with C/C++ and assembly language, particularly for test development, modeling, or debug
• Solid understanding of AMBA bus protocols (e.g., AXI, AHB, APB)
• Proficiency in scripting languages such as Python and/or Perl for automation and productivity
• Strong communication skills and the ability to work effectively as part of a global, cross‑functional team
• Demonstrated leadership skills, with the ability to mentor junior engineers and drive verification best practices
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Nice To Haves

• Knowledge of low‑power design concepts and power management techniques is a strong plus
• Experience with gate‑level simulation (GLS) and timing‑aware verification is a plus

Responsibilities

• Verify IPs, subsystems, and SoCs used across Qualcomm Wi‑Fi, connectivity, and IoT platforms
• Explore and apply innovative design verification methodologies, including simulation, formal verification, and emulation, to continuously improve testbench quality and efficiency
• Own end‑to-end low‑power verification, including testbench architecture, test plan development, and coverage-driven verification closure
• Collaborate with cross‑geography teams on IP, SoC, and verification infrastructure deliveries, including milestone planning and critical debug activities
• Serve as a technical point of contact for IP and SoC design teams, providing verification guidance and support
• Work closely with cross‑functional stakeholders to ensure the delivery of high-quality, robust IPs to SoC product teams

What This Job Offers

• Job Type: Full-time
• Career Level: Senior