Senior Emulation Engineer

Marvell Technology•Santa Clara, CA

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Infrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the award-winning OCTEON Fusion-M® product families. The SoC family of multi-core CPU processors and Radio Access SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform. As part of the Infrastructure Processor unit at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers’ specifications whether they’re a major telecom organization or automotive company, etc. What You Can Expect - Lead the development of complex SoC emulation models, including design integration, environment setup, compilation, and debug across industry‑leading platforms (e.g., Veloce, ZeBu, Palladium). - Drive emulation bring‑up activities, including clock/reset sequencing, firmware boot, and system validation using pre‑silicon hardware models. - Create and execute emulation test plans to support verification, performance analysis, software development, and system validation needs across multiple teams. - Collaborate closely with RTL design, verification, and firmware teams to define requirements, develop accurate hardware models, and ensure seamless integration into the emulation environment. - Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions. - Optimize emulation performance, including model partitioning, timing, and runtime efficiency. - Automate flows and improve productivity through scripting (Python, Perl, Tcl, shell) and tooling enhancements. - Interface with EDA vendors (Synopsys, Cadence, Siemens) to evaluate tool capabilities, resolve technical issues, and drive feature improvements. What We're Looking For - BS in Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of emulation experience (or MS/PhD with 5+ years of experience). - Experience with SystemVerilog and UVM. - Extensive knowledge of emulation platform offerings from leading vendors such as Synopsys, Cadence, and Siemens, with deep experience in building complex SoC emulation models. - Hands-on experience developing emulation models using platforms from Synopsys, Cadence, and Siemens is required. - Proficient in emulation bring-up, including reset sequence execution and firmware bring-up. - Strong working knowledge in one or more of the following areas: processor architecture, SoC components, interconnect buses, I/O protocols (PCIe, CXL, Ethernet), and memory interface technologies (DDR, HBM). - Skilled in scripting languages such as Perl, Python, Tcl, and UNIX shell. - Proven ability to define emulation strategy and platform requirements, develop emulation test plans, and drive verification execution for large-scale products on platforms such as Veloce, ZeBu, and Palladium. - Good programming skills, especially in C++ and ARM assembly. Other Skills: - Diligent, detail‑oriented, and able to take initiative and handle assignments with minimal supervision. - Able to work effectively with differing opinions and collaborate constructively. - Open-minded and adaptable; not rigid in approach or thinking. - Able to learn quickly and operate in a fast‑paced environment.

Requirements

BS in Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of emulation experience (or MS/PhD with 5+ years of experience).
Experience with SystemVerilog and UVM.
Extensive knowledge of emulation platform offerings from leading vendors such as Synopsys, Cadence, and Siemens, with deep experience in building complex SoC emulation models.
Hands-on experience developing emulation models using platforms from Synopsys, Cadence, and Siemens is required.
Proficient in emulation bring-up, including reset sequence execution and firmware bring-up.
Strong working knowledge in one or more of the following areas: processor architecture, SoC components, interconnect buses, I/O protocols (PCIe, CXL, Ethernet), and memory interface technologies (DDR, HBM).
Skilled in scripting languages such as Perl, Python, Tcl, and UNIX shell.
Proven ability to define emulation strategy and platform requirements, develop emulation test plans, and drive verification execution for large-scale products on platforms such as Veloce, ZeBu, and Palladium.
Good programming skills, especially in C++ and ARM assembly.
Diligent, detail‑oriented, and able to take initiative and handle assignments with minimal supervision.
Able to work effectively with differing opinions and collaborate constructively.
Open-minded and adaptable; not rigid in approach or thinking.
Able to learn quickly and operate in a fast‑paced environment.

Responsibilities

Lead the development of complex SoC emulation models, including design integration, environment setup, compilation, and debug across industry‑leading platforms (e.g., Veloce, ZeBu, Palladium).
Drive emulation bring‑up activities, including clock/reset sequencing, firmware boot, and system validation using pre‑silicon hardware models.
Create and execute emulation test plans to support verification, performance analysis, software development, and system validation needs across multiple teams.
Collaborate closely with RTL design, verification, and firmware teams to define requirements, develop accurate hardware models, and ensure seamless integration into the emulation environment.
Debug complex SoC and subsystem issues across RTL, firmware, emulation platforms, and toolchain interactions.
Optimize emulation performance, including model partitioning, timing, and runtime efficiency.
Automate flows and improve productivity through scripting (Python, Perl, Tcl, shell) and tooling enhancements.
Interface with EDA vendors (Synopsys, Cadence, Siemens) to evaluate tool capabilities, resolve technical issues, and drive feature improvements.