Senior Formal Verification Engineer

NVIDIA

16h

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people! Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Join us and discover how you can build a lasting impact on the world! As a Senior Formal Verification Engineer at NVIDIA, you will verify ASICs developed at the forefront using formal verification tools. You will define the verification scope and ensure correctness. You will employ sophisticated formal techniques to acquire sufficiently bounded proofs while working with architects, designers, and pre- & post-silicon verification teams to accomplish your tasks, as well as improve formal verification methodologies and flows. You will efficiently complete the formal verification effort for the entire project cycle, delivering high-quality results on schedule, and clearly conveying those results to the team. What you will be doing: Main task: Verify AI-related sophisticated ASIC designs & features with formal verification methods. Multi-functional Collaboration: Partner with architecture/RTL teams to specify properties, resolve deep design issues, and influence micro-architecture decisions. Formal verification execution: Leverage and unleash the power of formal verification to rigorously verify critical design properties and ensure compliance with specifications, as well as minimize spec ambiguities. Articulate formal verification coverage to partners Methodology Leadership: Develop and implement advanced formal verification environments and methodologies for complex ASIC designs, including automated flows for scalability and efficiency Mentorship: Train and coach junior engineers on formal techniques and standard processes; Help on methodology/FAQ documentation. Support silicon bring-up and debug using formal methods where it applies.

Requirements

BS/MS/PhD or equivalent experience in CS/CE/EE.
12+ years in ASIC verification with 8+ years focused on formal verification methods
Mastery of SystemVerilog Assertions (SVA) and formal property verification
Proficient on at least one popular formal verification tool in the industry(JapserGold, VC Formal, etc.)
Good scripting skills for flow automation(tcl, python, etc.)
Good written and oral communication skills
Keen attention to details

Nice To Haves

Shown success in full-cycle formal sign-off for complex designs
Expertise in formal apps: FPV apps, sequential equivalence checks, datapath verification, etc.
Deep understanding of GPU or LPU architecture/design

Responsibilities

Verify AI-related sophisticated ASIC designs & features with formal verification methods.
Partner with architecture/RTL teams to specify properties, resolve deep design issues, and influence micro-architecture decisions.
Leverage and unleash the power of formal verification to rigorously verify critical design properties and ensure compliance with specifications, as well as minimize spec ambiguities. Articulate formal verification coverage to partners
Develop and implement advanced formal verification environments and methodologies for complex ASIC designs, including automated flows for scalability and efficiency
Train and coach junior engineers on formal techniques and standard processes; Help on methodology/FAQ documentation.
Support silicon bring-up and debug using formal methods where it applies.