Senior High-Speed Analog Layout Engineer
About The Position
Senior High-Speed Analog Layout Engineer Locations: Irvine, San Jose, Austin or remote US Citizen or US Permanent Resident preferred Full-time Employee + Bonus, Benefits, 401k, Stock Options Responsibilities Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.) Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus) Required Minimum 5+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred) At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16) Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules Experience working in collaborative environments with international and remote teams Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams Experience using revision control systems for layout design management Preferred Exposure to optical or high-speed analog interfaces is a strong plus Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization Proven ability to collaborate with international teams (U.S., Canada, Argentina) Strong organizational skills with high attention to detail and follow-through Ability to multi-task and prioritize in a fast-paced, dynamic environment Proactive, eager-to-learn mindset with excellent problem-solving skills
Requirements
- Minimum 5+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
- Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
- At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
- Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
- Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
- Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
- Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
- Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
- Experience working in collaborative environments with international and remote teams
- Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
- Experience using revision control systems for layout design management
Nice To Haves
- Exposure to optical or high-speed analog interfaces is a strong plus
- Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
- Proven ability to collaborate with international teams (U.S., Canada, Argentina)
- Strong organizational skills with high attention to detail and follow-through
- Ability to multi-task and prioritize in a fast-paced, dynamic environment
- Proactive, eager-to-learn mindset with excellent problem-solving skills
Responsibilities
- Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
- Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
- Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
- Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
- Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
- Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
- Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
Benefits
- Bonus
- Benefits
- 401k
- Stock Options
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
