Senior IC Verification Engineer

Broadcom • Fort Collins, CO

1d

About The Position

The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements for AI and storage chips. The engineer will be responsible for a variety of advanced verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM) designing verification components such as UVM agents and behavioral models implementing coverage and assertions using System Verilog developing random & directed test cases against the specification This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing coverage results. Candidate must be a highly productive individual contributor with a demonstrated technical capability in system and sub-block level verification.

Requirements

• Excellent communication and interpersonal skills
• Demonstrated experience effectively communicating in a matrix organization to achieve common goals
• Demonstrated expertise in HDL languages Verilog/VHDL and SystemVerilog
• Expertise in designing in constrained random environments using UVM, OVM, or VMM.
• Experience running and debugging using HDL simulators
• Demonstrated familiarity with OOP languages (C++, Java, etc.) and Proficient with OOP techniques
• Demonstrated critical thinking to conceive and develop innovative solutions to solve complex engineering problems
• Demonstrated leadership skills
• Act independently to determine methods and procedures on new or special assignments
• Must have legal authorization to work in the US
• Bachelors in EE, CE, or CS and 12+ years of related experience; or Masters degree in EE, CE, or CS and 10+ years of related experience

Responsibilities

• verification environment development using modern verification techniques (System Verilog and UVM)
• designing verification components such as UVM agents and behavioral models
• implementing coverage and assertions using System Verilog
• developing random & directed test cases against the specification
• analyzing and debugging simulation failures
• analyzing coverage results

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time
• The company follows all applicable laws for Paid Family Leave and other leaves of absence.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior