Senior Mask Layout Engineer

IonQ

12d•$110,336 - $144,459•Remote

About The Position

IonQ is developing the world's most powerful full-stack quantum computer based on trapped-ion technology. We are pushing past the limits of classical physics and current supercomputing technology to unlock a new era of computing. Quantum computing has the potential to impact every area of human society for the better. IonQ’s computers will soon redefine industries like medicine, materials science, finance, artificial intelligence, machine learning, cryptography, and more. IonQ is at the forefront of this technological revolution. We are looking for a Senior Mask Layout Engineer on the Fab Tapeout and Validation Team. As a Senior Mask Layout Engineer, you’ll be part of a cross-functional team whose mission is to lead IonQ on its journey to build the world’s best quantum computers to solve the world’s most complex problems. In this role, you will be the owner of full-reticle tapeouts for use in trapped-ion quantum computers, which could include both photonic and analog electronic layers. In addition, you will help develop and maintain the internal PDK and circuit layout libraries, as well as write scripts to automate the layout of masks for tapeouts. You will also have the opportunity to work closely with the photonic and ion trap design and testing teams to help develop new and game-changing quantum technology to enable scalable quantum computing, memory, and networking. The Fab Tapeout and Validation Team is a remote-friendly team and this role can be performed remotely or in-person at IonQ’s College Park, MD or Bothell, WA campuses.

Requirements

Bachelor’s degree in Photonics, Physics, Electrical Engineering, or related field, or equivalent practical experience
Knowledge of semiconductor manufacturing processes and techniques
Excellent programming and software skills, including development in an IDE, proficiency with version control software, shell scripting, and code documentation
2+ years of experience with Python-based mask layout software packages such as Luceda IPKISS, GDSFactory, or Klayout

Nice To Haves

M.S. or Ph.D. in Photonics, Physics, Electrical Engineering, or related field
5+ years experience in generating layout files for complex semiconductor flows with custom elements, such as MEMS, integrated photonics, or superconducting circuits
Past ownership of full-reticle tapeouts with commercial foundries
Experience with commercial simulation, verification, and layout environments such as Synopsys, Cadence, and Ansys
Familiarity with photonic and/or analog electronic device principles including design, test, and fabrication
Proficiency in physical verification including DRC, LVS, and ERC
Experience with semiconductor and/or photonic workflows for tapeout with commercial foundries
Excellent verbal and written communication skills
A meticulous attention to detail and excellent track record of documenting requirements, implementation plan, and tracking progress
Ability to work independently, prioritizing tasks and managing time effectively in a deadline-oriented environment

Responsibilities

Conduct Python-based layout for full-reticle tapeouts with commercial foundries
Develop and maintain internal component PCell and automated circuit layout libraries
Interface with designers, test engineers, packaging engineers, and foundry team to define layout rules and component designs
Implement physical verification checks of layouts, including DRC and LVS
Develop detailed documentation of tapeouts and lead layout reviews with other team members
Work with cross-functional teams to understand circuit requirements and make recommendations to improve design, layout, and test workflows