Senior Mixed-Signal IC Design Engineer

K2 Space

19h • $170,000 - $250,000

About The Position

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply.

We are seeking a highly skilled Senior Mixed-Signal IC Design Engineer with strong expertise in high-speed data converter (ADC/DAC) and Phase-Locked Loop (PLL) design, particularly in advanced FinFET technology nodes. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will architect, develop, and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have flown your sub-system in space and developed cutting-edge mixed-signal SoCs.

Requirements

• M.S. or Ph.D. in Electrical Engineering with a strong focus in analog/mixed-signal IC design.
• 5+ years of relevant industry experience in mixed-signal circuit design.
• Proven hands-on experience in high-speed ADC/DAC designs with deep understanding of architectures, performance metrics, and design trade-offs.
• Strong knowledge of PLL design principles, including charge pump, VCO, loop filter, multi-modulus divider, sigma delta modulator, and jitter analysis.
• Solid understanding of FinFET CMOS process characteristics and layout parasitic considerations.
• Proficient in EDA tools such as Cadence Virtuoso, Spectre, behavioral modeling (Verilog-A, Verilog-AMS, MATLAB), and similar tools.
• Strong debugging, problem-solving, and communication skills.

Nice To Haves

• Familiarity with various RF transceiver architectures and their trade-offs, systems specifications, and ability to translate system requirements into circuit requirements.
• Tape-out experience in advanced FinFET nodes.
• Familiarity with digital calibration techniques and DSP-assisted mixed-signal systems.
• Solid understanding of and experience with building block circuits such as bandgaps, bias generators, TIAs, op-amps, filters, and LDOs.
• Exposure to EM/Reliability/ESD design best practices.
• Experience working in cross-functional, geographically distributed teams.

Responsibilities

• Design and develop high-performance, high-speed ADC and DAC architectures.
• Architect and implement low-jitter, low-power integer-N and fractional-N PLLs, frequency synthesizers and clocking systems.
• Engage with cross-functional analog, digital, DV, firmware, SoC architecture, technology, packaging, silicon validation, production test, and manufacturing teams to implement circuits and sub-systems.
• Drive full lifecycle design including specification, modeling (Verilog-A/AMS), schematic design, simulation, post-layout verification, and silicon validation.
• Perform design optimization for power, area, and performance in advanced FinFET nodes.
• Develop and maintain design documentation and support post-silicon bring-up and characterization.
• Support your product through production and spaceflight.
• Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Benefits

• Comprehensive benefits package including unlimited paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level