Senior Physical Design Integration Engineer

Intel • Folsom, CA

1d • Hybrid

About The Position

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. The Physical Design Integration Engineer performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. Works intimately with industry EDA vendors to build and enhance tool capabilities to design a highspeed, lowpower synthesizable CPU. Optimizes CPU design to improve productlevel parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation. Responsibilities The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc Responsibilities may also include defining design requirements such as frequency, operating voltages, power, etc. to achieve optimized designs on new technologies, processes and architectures The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems Good leadership and communication skills are necessary due to the nature of the work, size and complexity of the products and the size of the team

Requirements

• A successful candidate will have proven experience demonstrating the following skills and behavioral traits:
• Bachelor's in Electrical/Computer Engineering with 15+ years relevant work experience, or Master's in Electrical/Computer Engineering with 12+ years relevant work experience
• The ideal candidate will be capable of leading a small team as well as interacting with architecture and design teams to improve IP and ultimate product quality and performance
• Experience in: Logic Design, VLSI/ASIC Design, Computer Architecture
• Current Industry Experience in one or more ASIC style design flows - floorplanning, clock construction, synthesis, place and route, static timing analysis, layout verification
• Experience with Unix/Linux, Perl and TCL in order to implement useable, flexible cshell/perl/tcl programs that automate tool/flow methodologies
• Good leadership and communication skills are necessary due to the nature of the work, size and complexity of the products and the size of the team

Responsibilities

• The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc
• Responsibilities may also include defining design requirements such as frequency, operating voltages, power, etc. to achieve optimized designs on new technologies, processes and architectures
• The candidate would be required to work closely with the rest of the project team members to resolve issues which arise during the design cycle and take the key learnings into the next product cycle

Benefits

• We offer a total compensation package that ranks among the best in the industry.
• It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel .

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level