Senior PLL Characterization Engineer

NVIDIA • Santa Clara, CA

2d

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. A Phase-Locked Loop (PLL) Characterization Engineer tests, analyzes, and validates PLL circuits after silicon fabrication. They ensure the circuits meet specifications for frequency range, jitter, lock time, and energy efficiency.

Requirements

• Technical Knowledge: Deep understanding of PLL architectures (Analog, Digital, Fractional-N, LC, Ring VCOs), feedback loop dynamics, and frequency synthesis.
• Lab Equipment Proficiency: Experience with Advantest 9300 platform, high-speed oscilloscopes, spectrum analyzers, and vector network analyzers.
• Automation/Scripting: Strong proficiency in Java and C++ to automate test equipment. Experience in analog/mixed-signal validation.
• Collaboration: Ability to work with design, systems, and product engineering teams to drive silicon from bring-up to mass production.
• Bachelor's degree in electrical engineering or equivalent experience and 12+ years of related experiences.

Responsibilities

• ATE based Testing & Validation: Perform hands-on, post-silicon characterization of PLLs and related IP (VCOs, charge pumps, dividers).
• Performance Metrics Optimization: Characterize and optimize performance metrics, including phase noise, jitter (RMS/peak-to-peak), lock time, frequency range, power supply rejection ratio (PSRR), and power consumption.
• Develop ATE programs using the Advantest 93000 platform to automate measurements.
• Operate bench equipment such as waveform monitors and frequency analyzers when necessary.
• Analyze large datasets and communicate important findings to the PLL development team.
• Work with DFT to ensure accurate test modes are implemented in the chip development phase and help drive ATE vector generation.
• Debug & Root Cause Analysis: Identify and fix silicon bugs, PVT (Process, Voltage, Temperature) marginalities, and noise coupling issues.
• Correlation: Correlate ATE measurements with simulation results and bench test results
• Documentation: Generate comprehensive characterization reports, test plans, and documentation for design validation teams and production teams.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior