Senior Principal ASIC DFT Engineer

Northrop Grumman•Morrisville, MD

About The Position

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. Northrop Grumman Mission Systems, Digital Technologies Group, is seeking an ASIC DFT Engineer to join our team of highly qualified, diverse individuals in Digital Technologies. Qualified applicant will become part of the Digital Technologies department, which specializes in product designs for a variety of applications from undersea to outer space. . This position will be in Morrisville, NC or Linthicum, MD. This position is contingent upon, the ability to obtain or maintain an active DoD Secret clearance.

Requirements

Bachelor’s degree with 8 years of experience, a Master’s degree with 6 years of experience or a Ph.D. with 4 years of experience in Science, Technology, Engineering, Mathematics, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree.
U.S. Citizenship is required
Ability to obtain/maintain an active secret clearance
Experience in full product life cycle of ASIC Design
Experience with Cadence and/or Mentor test insertion and ATPG tools
Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTA
Experience with memory BIST and logic BIST
Experience generating test patterns and analyzing and debugging test failures
Experience working with test engineers to implement ATPG vectors on tester hardware
Proficiency in HDL (VHDL/Verilog/SystemVerilog) and scripting languages such as Tcl, Python or Perl

Nice To Haves

Master's Degree in Electrical or Computer Engineering
Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus
Active DoD Secret Clearance or higher

Responsibilities

Responsible for all aspects of DFT (Design for Test) for ASIC designs
Responsible for defining the overall test strategy and test plan
Responsible for developing DFT architecture and implementation, including scan, logic BIST, memory BIST and repair, hierarchical test, boundary scan, and ATPG
Responsible for advanced DFT methodology and flow development