About The Position

Join our high‑performance Silicon Validation team and play a key role in enabling next‑generation high‑speed FPGA/PLD devices with a strong focus on ARM core, memory management and cache coherency protocols, high speed peripherals (USB31 Gen2, Ethernet with TSN, USB2.0 etc.), low speed peripherals (I3C, I2C, SPI, UART etc). You will drive device‑level and Digital IP validation, platform development, and infrastructure enablement to ensure industry‑leading quality, reliability, and performance. This role provides the opportunity to work hands‑on with advanced high‑speed serial interfaces, collaborate across multiple engineering teams, and influence the architecture of future FPGA products.

Requirements

  • Bachelor’s / master’s degree in electrical & Electronics Engineering (BSEE) or related field.
  • 8+ years of hands-on experience in FPGA or ASIC silicon validation methodology, test planning, test development and debug
  • 8+ years of experience in FPGA validation methodologies with hands‑on experience in system validation and debug
  • 3+ years of experience in ARM protocol, cache coherency protocol, link training, equalization, protocol compliance, and high‑speed serial signaling; familiarity with next‑generation Peripheral standards is a strong advantage.
  • 3+ years of experience in FPGA architecture (advantage).
  • 3+ years of experience or familiarity with programming languages such as Python and Verilog (plus).

Responsibilities

  • Develop comprehensive validation strategies for high‑speed FPGA devices and the general-purpose processors(ARM core) to manage the system memory access, peripheral access, interrupt handling etc. for the FPGA Digital IP, aligning with technical, architectural, and business requirements.
  • Develop content and run on Emulation.
  • Utilize industry‑leading Protocol Exerciser/Analyzer solutions for validation, traffic generation, error injection, and trace analysis.
  • Perform timing characterization, compliance/conformance checks, and performance validation according to specifications.
  • Drive innovation in validation methodologies, automation flows, test platforms, and infrastructure to enhance scalability, efficiency, and throughput for future PCIe generations.
  • Collaborate on high‑speed PCB design, contributing to design of evaluation boards for device, platform, and IP validation.
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