Senior SoC Design Engineer, Cloud

Google•Sunnyvale, CA

1d•$156,000 - $229,000

About The Position

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be working on SoC-level RTL design for our data center accelerators. You will work on top-level RTL, architecture, design and implementation of global communication busses, and integration of ASIC designs. You will interact with numerous ASIC development teams. You will own deliverables to the cross-functional teams (i.e. Physical Design, Verification, Validation, Firmware) at various project milestones. You will also be directly involved in defining and creating methodologies that enable a highly efficient design environment for all ASIC engineers. As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your experience in digital logic design, computer architecture, and RTL coding to create efficient hardware solutions. This position offers the opportunity to manage technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with RTL coding using Verilog/SystemVerilog.
Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with scripting languages (i.e. Tcl, Python or Perl).
Experience architecting RTL solutions employing software based construction, instantiation, customization and generation of RTL.
Experience with SOC implementation standards and interfaces (i.e. AXI).
Experience with CDC, RDC, RTL Linting and LEC.
Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines, and bus protocols.

Responsibilities

Define and document the microarchitecture for digital designs within the TPU.
Write high-quality, performant, and power-efficient register transfer level (RTL) code, primarily in SystemVerilog.
Collaborate with the verification team to develop test plans, debug RTL, and ensure functional correctness.
Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
Contribute to the development and enhancement of design tools, flows, and methodologies.