Senior Staff DFT Engineer

Renesas Electronics•Austin, TX

75d•Hybrid

About The Position

About the team: As part of Renesas’s Infrastructure Power Business, you will contribute to the development of our next-generation digital power management ICs. These are mixed-signal, MCU-based SOC designs that power cloud computing in the datacenter. What we need: We are seeking a Mixed-Signal DFT Engineer to ensure efficient, high-coverage, testability for analog and mixed-signal designs.

Requirements

SystemVerilog
Cadence Virtuoso
Working understanding of C/C++ programming experience for microcontrollers.
Fundamental understanding of mixed-signal design blocks: ADC’s/DAC’s, etc
Understanding of ATE test time costs and hardware/tester limitations
10 years of experience
Bachelors/Masters Electrical Engineer or Computer Engineering

Nice To Haves

Familiarity with Firmware, ATE program structure and capabilities is a plus
Familiarity with Lab/bench validation

Responsibilities

Own the test plan for all analog and mixed signal content
Ensure integrity in observability and controllability of each design block to/from the pins of the part
Ensure all blocks can be tested in a timely manner
Ensure as many blocks as possible can be tested in parallel on-chip with minimal tester interaction
Ensure calibration and trim routines can be efficiently generated
Create definitions and procedures for block testing that can be used for ATE test generation
Specify test, trim and calibration requirements for analog circuits blocks such as PLLs, DLLs, ADCs and DAC’s
Test interfaces
Logic controls
Self-test and firmware-based test routines
Modify block schematics and behavioral models as needed to implement testability features
Write Firmware to exercise test routines
Simulate test routines to demonstrate adherence to parametric block specs with process, voltage, temperature variations and noise
Bench testing of test patterns and firmware prior to transfer to ATE
Coordinate with other Engineering disciplines
Design to ensure DFT approach is effective and efficient (silicon area cost < test time savings)
Firmware to ensure trim procedures can be efficiently uploaded and run at test
Verification to ensure all functions and trims can be tested using firmware/DFT test modes
ATE Test to ensure all test hardware requirements are correct and up to date, and to ensure that DFT simulations are easily transferable to ATE methods