Senior Staff Engineer, Digital Verification – ACAS

Saige Partners • San Jose, CA

21h

About The Position

The Senior Staff Engineer, Digital Verification – ACAS is responsible for defining and executing verification strategies for complex digital designs at both block and full-chip levels. This role collaborates closely with RTL designers and system architects to develop verification specifications, build advanced test environments, and ensure design functionality, performance, and quality through comprehensive simulation and analysis. The ideal candidate brings deep expertise in processor verification, strong debugging skills, and experience with modern verification methodologies and EDA tools. This is a contract position and is not eligible for C2C or W2 referral candidates.

Requirements

• Bachelor’s degree in Electrical Engineering or a related field with 15+ years of relevant industry experience; OR Master’s degree with 13+ years of experience; OR PhD with 10+ years of experience.
• Strong experience developing verification test benches using SystemVerilog UVM.
• Proven expertise in constrained-random and directed test development.
• Experience in MCU/CPU verification at processor and subsystem levels.
• Strong understanding of CPU architectures and instruction sets, including:
• x86
• ARM
• RISC-V variants
• Experience with:
• Core architecture and micro-architecture verification
• Multi-processor cache coherency (L2/L3)
• Memory hierarchy verification
• Strong analytical and troubleshooting skills.
• Ability to quickly learn and apply new verification techniques and methodologies.
• Effective collaboration and communication skills in cross-functional engineering environments.

Nice To Haves

• Strong object-oriented programming skills in C++ and SystemVerilog.
• Proficiency with scripting languages such as Python and/or Perl.
• Familiarity with Formal Verification methodologies.
• DMS verification experience or knowledge preferred.
• Excellent simulation debugging and problem-solving abilities.
• Experience with industry-standard EDA tools, including:
• Simulators: Synopsys VCS, Cadence Xcelium, Siemens QuestaSim (or equivalent)
• Debugging tools: Synopsys Verdi, Cadence SimVision

Responsibilities

• Collaborate with RTL Designers and System Architects to define verification requirements and specifications.
• Design and implement verification test suites for both full-chip and block-level validation.
• Develop directed and constrained-random test cases using SystemVerilog UVM methodologies.
• Analyze and debug simulations at RTL and gate levels to identify and resolve design issues.
• Develop functional coverage models and collect, analyze, and report coverage metrics.
• Build and maintain verification test benches for low-power designs, including Hybrid UPF and PG netlist simulations.
• Manage regression testing activities and analyze regression results.
• File, track, and manage defects using bug tracking systems.
• Promote adoption of new verification methodologies, tools, and best practices across engineering teams.

What This Job Offers

• Career Level: Mid Level