About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell Physical Design team is located in our Burlington, VT office, and has a long history of successful design tapeouts in advanced process nodes. Our team is made up of both newer and more experienced engineers with a broad depth of static timing analysis and physical design engineering experience. Being a part of our team will give you a chance to work on many different aspects of the chip design process, while working alongside some of the best engineers in the industry. In this unique role, you’ll have the opportunity to work on both the timing analysis and methodology for future designs of our next-generation, high-performance processor, and data center chips in a leading-edge CMOS process technology. This role is based in the Marvell office in Burlington, VT. Working from another location is not offered. Relocation for qualified candidates will be provided. You will work with both local and global STA team members on the timing analysis and timing closure of complex chips, as well as the methodology to enable an efficient and robust design process.
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Job Type
Full-time
Career Level
Mid Level
Number of Employees
1,001-5,000 employees