Senior Technologist, Hardware Development Engineering -

Western Digital•Roseville, CA

4d•Onsite

About The Position

We are seeking an Expert-level Hardware Engineer who is equally strong in board-level hardware design and ASIC interface / integration (I/O, package, power integrity, DFT/test, analog, and signal integrity). This is a hands-on role for a recognized subject matter expertise in delivering complex hardware from concept through production, including deep lab bring-up and root-cause complex issues, able to debug across silicon, package, and board.

Requirements

Professional hardware engineering experience.
Proven ownership of multiple complex programs through the full lifecycle: architecture → design → build → bring-up → debug → qualification → production ramp → sustaining.
Demonstrated, hands-on experience spanning both: Board/system hardware design (schematic ownership, layout partnership, bring-up, debug, standards compliance, manufacturing support)
ASIC I/O and integration (I/O architecture decisions, package/substrate considerations, PI/SI co-design, tape-out support, DFT/test hooks)
Hands-on experience integrating and debugging leading-edge Ethernet and PCIe interfaces, including: 100G/200G Ethernet PAM4 transceivers (system/channel design, equalization concepts, BER/PRBS testing, standards compliance planning and test)
PCIe Gen 6 (system/channel design, equalization concepts, BER/PRBS testing, standards compliance planning and test)
Demonstrated ability to design and simulate high-speed links across die/ASIC package/PCB/connectors/cabling, balancing SI/PI/EMI and manufacturing constraints.
Proven experience designing complex boards using cutting-edge FPGAs (e.g., high-end families with high-speed transceivers), including: Power architecture and sequencing for FPGA multi-rail systems
High-speed transceiver channel design, with associated reference clock design, reset/boot/strap
Bring-up and debug using vendor tools, link training, PRBS/IBERT-style testing, and lab correlation
Ownership of FPGA-based platform bring-up from first power-on through high-speed link validation and system integration.
Expert schematic design and review for high-complexity boards (compute/networking/accelerator-class or equivalent).
Strong experience with: Multi-rail power distribution networks (frequency domain impedance control, sequencing, fault handling)
High-speed interfaces (DDR, PCIe, Ethernet/SerDes-based links, USB, I2C, SPI, MIPI—based on product needs)
Controlled impedance trace design (understanding manufacturing and cost tradeoffs)
Clocking/reset/fault tolerant architectures and debug access design
General analog circuit design
Proven partnership with layout teams to define and enforce: Stackups, reference planes, return paths, via design and strategy, routing constraints
Differential pair controlled impedance routing, channel constraints, connector strategy, manufacturability
SI design experience: Insertion loss, return loss, eye/jitter concepts, electrical noise abatement, termination, discontinuities, correlation of models to measurements.
Deep PI/PDN experience: target impedance approach, decap strategy, anti-resonance mitigation, transient response, measurement and correlation.
Practical EMI/EMC grounding/shielding/filtering understanding grounded in design and lab realities.
Ability to own or co-own ASIC I/O choices: I/O standards, voltage domains, ESD strategy, drive/slew tuning, noise coupling/SSO considerations
Strong understanding of package/substrate impacts: Pinout/ballout tradeoffs, escape routing constraints, lane swapping realities
Package parasitics effects on SI/PI and timing margins
Thermal/mechanical considerations influencing reliability and assembly
Power architecture competence spanning system and ASIC-aware constraints (noise isolation, domain partitioning, bring-up hooks).
Strong working knowledge of DFT concepts and productization: JTAG/boundary scan, scan/ATPG fundamentals, BIST/loopbacks/PRBS, on-chip monitors/telemetry
Experience defining debug and manufacturing test strategy: Test access, test point strategy, coverage vs SI impact, failure analysis workflows
Practical capability to own/review analog subsystems relevant to high-performance designs: Clock generation/distribution and jitter sensitivity
Filtering/biasing, stability fundamentals, measurement integrity/noise coupling
Mixed-signal partitioning and grounding strategy
Expert in structured bring-up and root-cause debug: Creation and execution of EVT test plan
High-speed measurement competence (Oscilloscopes, BERT, network analyzers, spectrum analyzers, probing strategy, fixtures, de-embedding awareness)
Ability to correlate bench measurements back to simulation and drive corrective actions
Familiarity with mainstream schematic/layout environments (e.g., Cadence/Altium/Mentor-class tools) and constraint-driven design practices.
Comfortable with SI/PI modeling workflows (IBIS/AMI, S-parameters, SPICE-level reasoning) and validation against lab data.
Strong documentation, design review, ECO, and risk-management discipline.
Operates as a cross-functional technical leader across silicon, package, board, validation, test, manufacturing.
Writes clear specs/constraints that prevent rework (I/O requirements, channel budgets, PDN targets, bring-up/test access).
Drives design reviews that identify real risks early and mentors engineers across experience levels.
Drive partnerships with key IP, component and manufacturers.
Examples where you personally identified high-speed margin failures (examples: 100/200G PAM4 and/or PCIe Gen 6 or slower data rates) through SI/PI analysis or lab testing.
Examples of cross-boundary root cause (ASIC ↔ package ↔ board) with measurable corrective actions.
Examples where you improved observability/DFT/test hooks to accelerate bring-up and production readiness.

Nice To Haves

Advanced packaging or multi-die systems (e.g., chiplets/interposers/HBM-class integration).
Ownership of qualification/compliance (EMC, safety, thermal/mechanical) and production yield improvement.
Experience with design for low cost, second-source strategies, and sustained field reliability initiatives.
AMD FPGA Knowledge preferred

Benefits

paid vacation time
paid sick leave
medical/dental/vision insurance
life, accident and disability insurance
tax-advantaged flexible spending and health savings accounts
employee assistance program
other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity
tuition reimbursement
transit
the Applause Program
employee stock purchase plan
the WD Savings 401(k) Plan