Senior Test and Validation Engineer, Silicon, Bringup

Google•Fremont, CA

2d•$183,000 - $271,000

About The Position

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will lead custom silicon bringup, Verilog code development, and Automated Test Equipment (ATE) engineering. You will be responsible for defining post-silicon validation specifications and executing in-depth debug, specifically focusing on microdisplay backplane validation.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in analog circuit design, including simulation and verification.
Experience working with relevant electronic design automation (EDA) tools for circuit design and analysis.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
10 years of experience in custom silicon design, with a focus on digital logic design, analog design and test, and DFT implementation.
Experience with advanced DFT techniques such as hierarchical DFT, compression, and diagnosis.
Experience with custom silicon bringup, leading test plan development, and performing in-depth silicon validation.
Proficiency in hardware description languages (e.g., Verilog, SystemVerilog).
Excellent problem-solving, communication, and teamwork abilities.

Responsibilities

Lead the bring-up process on debugging stations, including, but not limited to, FPGA-based platforms.
Additionally, assist in the analysis of silicon failures and collaborate with design and test engineering teams to ascertain root causes.
Advocate enhancements in the silicon validation flow, encompassing new tools, methodologies, and scripts, to significantly boost efficiency and coverage.
Forge partnerships with the Architecture, Physical Design, and Test Engineering teams to guarantee seamless integration and execution of the Design-for-Test (DFT) plan.
Architect, design, and implement digital logic utilizing Verilog or System Verilog, deriving from high-level specifications.
Collaborate with the verification team to meticulously define test plans, formulate assertions, and debug logic issues.