Key Responsibilities: Design and implement sensor timing control logic and contribute to ISP system-level integration Participate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/performance/area (PPA) trade-offs Integrate and validate ISP data paths based on PRD, design specifications, and overall SoC architecture Collaborate closely with CIS project leads and sensor digital/analog engineers for system integration and validation Work with physical design teams on floor planning, timing closure, and DFT implementation Perform full-chip integration and verification Support chip bring-up, validation, and silicon debugging Collaborate with algorithm and application engineers on image tuning, optimization, and qualification Support silicon validation, debugging, and image quality tuning through production readiness
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Job Type
Full-time
Career Level
Mid Level