Sr Digital Synthesis Engineer, HBM

Micron Technology • Richardson, TX

8d

About The Position

Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of hands‑on experience in digital synthesis and timing closure.
• Strong understanding of:
• Digital logic design and micro‑architecture
• Static Timing Analysis (STA)
• Low‑power design techniques and power intent formats
• ASIC/SoC design flows from RTL to GDS
• Proven ability to independently own synthesis for complex blocks or full chips.

Nice To Haves

• Experience with high‑performance or low‑power SoCs.
• Understanding of physical synthesis and congestion‑aware optimization.
• Knowledge of clocking architectures and CDC/RDC considerations.
• Scripting skills in Tcl, Python, or Perl to automate synthesis flows.

Responsibilities

• Own logic synthesis, optimization, and constraint development for large digital blocks or full SoCs.
• Translate RTL and architectural intent into timing‑clean, area‑efficient, and low‑power gate‑level netlists.
• Develop and maintain SDC constraints including clocks, generated clocks, CDC paths, false paths, and multicycle paths.
• Perform QoR analysis (timing, area, power) and drive improvements across synthesis iterations.
• Drive pre‑ and post‑synthesis timing closure across all modes and PVT corners.
• Optimize designs for power (UPF/CPF), area, and performance using advanced synthesis techniques.
• Analyze and fix timing violations, congestion issues, and synthesis‑related ECOs.
• Support power‑aware synthesis, clock gating, and multi‑voltage designs.
• Work closely with RTL designers to improve code quality, synthesizability, and performance.
• Collaborate with physical design teams on floorplanning assumptions, timing budgets, and handoff readiness.
• Partner with DFT teams to ensure scan, test, and synthesis flows are aligned.
• Support formal equivalence checking (LEC) between RTL and synthesized netlists.
• Deliver synthesis‑clean netlists ready for place and route.
• Support ECO flows, metal‑only fixes, and late‑stage timing updates.
• Participate in tape‑out reviews, ensuring synthesis assumptions and constraints are correct and complete.

Benefits

• Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.
• We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time-off program and paid holidays.
• For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level