Sr. FPGA Modem and Physical Layer Development Engineer, Amazon Leo

Amazon • Austin, TX

4d

About The Position

Create high-performance FPGA solutions to support next-generation modem systems
from LEO satellites. This is a unique opportunity to define and implement a
state-of-the-art wireless communication system with a focus on an ultra-reliable
low-latency, high-throughput physical layer (PHY). The FPGA Design Engineer will
work closely with systems teams to define, develop, and release FPGA-based
signal processing and modem solutions using latest generation hardware and
modern design methodologies.

In this role, you will design, implement, and support a wireless modem on a
ARM/FPGA system-on-chip platform. Key responsibilities include:
• End-to-End RTL Development: Create and release RTL code through the full
development lifecycle: system architecture definition, RTL design, physical
implementation, timing closure, and simulation validation.
• System Integration: Collaborate with Digital Communications and RF system
architects to implement complex logic functions such as signal detection and
synchronization, channel coding (LDPC/Polar), beamforming, or massive MIMO
processing.
• Cross-Functional Collaboration: Work with HW, FW, and SW teams to bring up and
test integrated systems combining FPGA, RF front-ends, and networking stacks.
• Architectural Trade-offs: Drive trade-off analysis to optimize FPGA resources
for cost, size, power, and performance to meet stringent 5G latency and
throughput requirements.
• Validation: Conduct lab-based silicon validation using high-speed signal
generators and analyzers to ensure modem performance meets throughput and
reliability metrics

Requirements

• Bachelor's degree or above in electrical engineering, computer engineering, or equivalent
• Experience with modern ASIC/FPGA design and verification tools
• Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs
• 7+ years of experience in FPGA design and implementation using System Verilog/Verilog/VHDL.
• Hands-on experience with Xilinx/AMD or Intel/Altera FPGAs

Nice To Haves

• Master's degree or Ph.D. degree in Electrical Engineering or related field
• Master's degree or above in electrical engineering, computer engineering, or equivalent
• Experience in embedded development in C/C++, or experience writing low level drivers
• Experience building and implementing wireless modem on ARM/FPGA SoCs, including familiarity with Physical Layer designs.
• Experience developing test venue software and hardware infrastructure for hardware-in-the-loop (HIL) testing environment.
• A proven track record of successfully fielding and supporting complex FPGA or ASIC based wireless products.

Responsibilities

• End-to-End RTL Development: Create and release RTL code through the full development lifecycle: system architecture definition, RTL design, physical implementation, timing closure, and simulation validation.
• System Integration: Collaborate with Digital Communications and RF system architects to implement complex logic functions such as signal detection and synchronization, channel coding (LDPC/Polar), beamforming, or massive MIMO processing.
• Cross-Functional Collaboration: Work with HW, FW, and SW teams to bring up and test integrated systems combining FPGA, RF front-ends, and networking stacks.
• Architectural Trade-offs: Drive trade-off analysis to optimize FPGA resources for cost, size, power, and performance to meet stringent 5G latency and throughput requirements.
• Validation: Conduct lab-based silicon validation using high-speed signal generators and analyzers to ensure modem performance meets throughput and reliability metrics

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level