Sr. Principal Application Engineer

Marvell Technology•Santa Clara, CA

6d•Onsite

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact You will join the Connectivity Business Unit at Marvell, a team responsible for delivering high-speed connectivity solutions that enable next-generation AI and cloud infrastructure. Our PCIe Applications Engineering team works directly with hyperscale cloud providers, system OEMs, and technology partners to deploy Marvell’s advanced PCIe interconnect solutions into large-scale data center environments. Acting as the technical front line between customers and engineering, the team supports product integration, resolves complex system-level issues, and ensures successful deployment of Marvell technologies across major cloud platforms. This group collaborates closely with: • Silicon Design and Systems Engineering • Product Line Management • Field Applications Engineers (FAEs) • Sales and Customer Engineering teams • Marketing and Technical Documentation teams Together, we help deliver connectivity solutions enabling massive GPU clusters and AI compute fabrics used by the world’s largest cloud providers. What You Can Expect As a Principal Applications Engineer, you will play a critical role enabling customers to successfully deploy Marvell’s PCIe interconnect technologies across next-generation AI and data center platforms. You will serve as the primary technical interface between key customers and Marvell engineering teams, helping drive design success, accelerate issue resolution, and influence future product development. Your work will directly impact the deployment of infrastructure powering AI clusters, hyperscale compute systems, and advanced data center architectures. Key areas of impact include: Enabling design-wins for Marvell PCIe interconnect products in next-generation AI platforms Supporting hyperscale customers deploying large-scale compute clusters Driving technical problem resolution that directly impacts product adoption and revenue Influencing Marvell’s product roadmap through direct customer engagement Mentoring and developing senior engineering talent within the applications team What Can You Expect This role offers the opportunity to work at the cutting edge of semiconductor technology and hyperscale infrastructure. You can expect to: Work directly with top hyperscale cloud companies and system OEMs building the world’s largest AI platforms Support deployment of advanced PCIe interconnect technologies including switches, retimers, bridges, and redrivers Solve complex system-level challenges involving high-speed interfaces, SerDes architectures, and AI infrastructure scaling Collaborate closely with silicon architects and design teams shaping next-generation products Participate in customer architecture reviews and design discussions Mentor senior and staff engineers supporting long-term product success Contribute to technical collateral including application notes, white papers, and system design guides This role requires in-office collaboration five days per week in Santa Clara, enabling tight interaction with engineering teams and rapid problem solving. Occasional travel to customer sites and industry events may be required.

Requirements

Bachelor’s degree in Electrical Engineering or related field with 12+ years of relevant experience, or Master’s / PhD in Electrical Engineering with 10+ years of industry experience
Technical Expertise Demonstrated experience in:
High-speed interface technologies and protocols
SerDes architectures and high-speed signal integrity
Mixed-signal integrated circuits
Digital signal processing (DSP) techniques used in high-speed communications
Hands-on lab experience with:
PAM4 SerDes TX/RX validation
High-speed test equipment including BERTs, oscilloscopes, and signal analyzers
Strong experience with PCIe interconnect technologies, including:
PCIe Switches
PCIe Retimers
PCIe Redrivers
PCIe Bridges
Proven experience working in Applications Engineering or customer-facing technical roles
Ability to analyze and resolve complex system-level technical issues
Excellent written and verbal communication skills
Ability to translate highly technical concepts into clear customer guidance
Prior experience mentoring senior and staff engineers
Strong ability to lead cross-functional technical problem solving
Comfortable working in highly collaborative environments spanning customers, engineering teams, and product management

Nice To Haves

Experience with C and/or Python programming is a plus
Experience with optical interconnect technologies is a strong plus
Mandarin language capability is preferred in addition to English

Responsibilities

Proactively support Marvell’s PCIe interconnect product portfolio
Serve as the primary technical interface between customers and Marvell engineering teams
Review customer system architectures and designs incorporating Marvell devices
Own and drive customer issues to resolution, including issue replication, debugging, and coordination with hardware, software, and systems engineering teams
Provide system-level support spanning hardware, firmware, and software environments
Deliver technical training and product demonstrations to customers, FAEs, and sales teams
Collaborate with product managers, marketing, and engineering teams to identify feature improvements and future product opportunities
Develop technical documentation including application notes, user guides, and technical white papers
Mentor and develop senior and staff engineers within the applications engineering organization