Sr. Staff Engineer, SoC RTL Design - Fabric
About The Position
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Sr. Staff SoC RTL Design Engineer specializing in Fabric to lead the architecture, implementation, and optimization of high-performance on-chip interconnects and fabrics for next-gen AI and compute workloads. This role is ideal for senior engineers with deep expertise in NoC and fabric microarchitectures who thrive at the intersection of RTL design, performance tuning, and scalable SoC integration. This role is hybrid, based out of Toronto, Boston, Ottawa or Santa Clara. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Requirements
- A senior digital design leader with deep expertise in on-chip fabric and NoC microarchitectures for high-performance SoCs.
- Proficient in RTL development (SystemVerilog/Verilog) for complex interconnects, with hands-on experience across full ASIC flows.
- Expert in PPA optimization for low-latency, high-bandwidth fabrics supporting AI workloads and multi-die integration.
- A collaborative technical driver skilled in spec definition, peer reviews, and cross-functional team planning.
- Experienced in prior on-chip fabric and NoC designs, including protocol compliance (e.g., AXI, CHI) and coherency mechanisms.
Responsibilities
- Lead architecture and RTL implementation of custom fabric IP, NoC routers, switches, and SoC interconnect components.
- Drive performance-aware design decisions for compute-heavy interconnects, ensuring scalability and efficiency.
- Contribute to validation flows using emulation, FPGA prototyping, or UVM to verify fabric functionality.
- Support synthesis, timing closure, power optimization, and clean handoffs to backend teams.
- Mentor junior engineers on fabric best practices, automation, and integration with CPU/memory subsystems.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Education Level
No Education Listed
