SSG Design Engineering Intern (Summer 2026

Cadence Design Systems • San Jose, CA

1d

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design Engineering Intern The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry leading Digital IP (intellectual Property), from processor cores and DSPs to Memory Controllers, to Network on Chip (NoC), to IO solutions. Our configurable and extensible IP solutions are designed to meet the demands of SOCs and Chiplets targeted at a wide range of applications. Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare. The Cadence SSG Team is hiring graduates to join our R&D teams in San Jose, CA. This is an amazing opportunity to work as a Design Engineering Intern at a world leader in computational software, semiconductor design IP, and system verification hardware. Come be part of this great SSG Team where you can make an impact that is visible. This Design Engineering Intern position involves working on Digital Design tasks, or Design Verification tasks related to the Janus NoC IP product. (a) Digital Design projects involve working on aspects of the logic design of the Janus NoC. It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating and debugging RTL logic, running synthesis, place & route and other Electronic Design Automation (EDA) tools to study and achieve timing, area, and power goals. (b) Design Verification Team projects involve working on aspects of the verification of the Janus NoC. Assist with developing test plans, writing functional tests (UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows. The Design Engineering intern will work closely with the Design, Verification, and Physical Design teams.

Requirements

• Currently enrolled in MS/BS program with major in Electrical Engineering, Computer Engineering, or a similar major.
• Deep understanding of Digital Design and/or Design Verification Fundamentals
• Excellent automation skills using Tcl, Perl, shell scripting
• Excellent oral and written communications skills

Nice To Haves

• Exposure to design automation tools is a plus

Responsibilities

• Digital Design projects involve working on aspects of the logic design of the Janus NoC.
• RTL implementation of a specified micro-architecture in System Verilog, simulating and debugging RTL logic, running synthesis, place & route and other Electronic Design Automation (EDA) tools to study and achieve timing, area, and power goals.
• Assist with developing test plans, writing functional tests (UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows.

What This Job Offers

• Career Level: Intern