Staff Process Integration Engineer

OMNIVISION • Santa Clara, CA

1d

About The Position

• Develop advanced CMOS image sensor (CIS) process to meet performance targets under a defined schedule and budget.
• Collaborate with foundry partners to define and improve the CIS silicon, color and package process for each CIS technology.
• Provide support to production and design teams to improve yield and overall sensor performance, establishing process flow applicable to mass production.
• Design and manage silicon split lots with respect to project goals and schedules to achieve performance targets, meet production requirements, and research and development of future technologies.
• Analyze and interpret large volumes of bench and wafer level data; feedback to pixel and wafer split design to optimize design and improve performance.
• Work in close collaboration with internal pixel design and characterization engineers, and external foundry partners; primary liaison between internal and external teams to drive effective technical communication and discussion.
• Work with characterization engineers to analyze data and test results, provide feedback on evaluation methods and settings to improve testing efficiency and accuracy; coordinate evaluation schedule and equipment to enable testing.
• Continuously track technology improvement and state of art developed by foundry; select and implement appropriate fabrication processes to meet CIS performance and yield targets; closely monitor lot processing and swiftly address/feedback any issues to foundry to mitigate product loss and schedule delay.

Requirements

• Master’s degree or foreign equivalent degree in Electrical Engineering, Computer Engineering, or a related field.
• Two years of experience in developing and fabricating semiconductor devices.
• Developing and fabricating semiconductor devices, including designing and managing experimental splits to achieve performance targets.
• Photolithography and microfabrication techniques (electron beam, thermal deposition, sputtering, reactive ion etching) in a clean room environment.
• Silicon and semiconductor device testing, including electron microscopy (SEM, TEM), atomic force microscopy (AFM), spectroscopy techniques (photo- and fluoro- luminescence, Fourier transform IR spectroscopy, UV-vis), and optical and electrical device characterization.
• Defining project roadmaps, performance targets, and schedules.

Responsibilities

• Develop advanced CMOS image sensor (CIS) process to meet performance targets under a defined schedule and budget.
• Collaborate with foundry partners to define and improve the CIS silicon, color and package process for each CIS technology.
• Provide support to production and design teams to improve yield and overall sensor performance, establishing process flow applicable to mass production.
• Design and manage silicon split lots with respect to project goals and schedules to achieve performance targets, meet production requirements, and research and development of future technologies.
• Analyze and interpret large volumes of bench and wafer level data; feedback to pixel and wafer split design to optimize design and improve performance.
• Work in close collaboration with internal pixel design and characterization engineers, and external foundry partners; primary liaison between internal and external teams to drive effective technical communication and discussion.
• Work with characterization engineers to analyze data and test results, provide feedback on evaluation methods and settings to improve testing efficiency and accuracy; coordinate evaluation schedule and equipment to enable testing.
• Continuously track technology improvement and state of art developed by foundry; select and implement appropriate fabrication processes to meet CIS performance and yield targets; closely monitor lot processing and swiftly address/feedback any issues to foundry to mitigate product loss and schedule delay.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level