Staff SOC Physical Design Engineer

QualcommAustin, TX
3d$161,179 - $210,000

About The Position

This individual leads, plans, synthesizes ambiguous or conflicting requirements and performs the complex responsibility of the Physical Design Flow of high-speed DDR, graphics, physical verification flows, micro-architecture, SOC algorithm design and modeling, and methodology, focusing on target power utilization and optimization for system-on-chip (SoC) products and how these features impact power and performance. Responsibilities include: Floor Planning, Clock Tree Synthesis, Place and Route, PDN, Timing analysis and closure. Performs various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels. Provides schedules and support cross-functional engineering effort to drive to signoff closure for tapeout. Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.

Requirements

  • Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field and three (3) years of experience in a related occupation.
  • Bachelor's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field and seven (7) years of progressive experience in a related occupation.
  • Employer will accept any suitable combination of education, training or experience.

Responsibilities

  • Floor Planning
  • Clock Tree Synthesis
  • Place and Route
  • PDN
  • Timing analysis and closure
  • Performs various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels.
  • Provides schedules and support cross-functional engineering effort to drive to signoff closure for tapeout.
  • Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.
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