TPU PCIe RTL Design Engineer

Google • Sunnyvale, CA

6d • $156,000 - $229,000

About The Position

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Join the team designing and developing the core components of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.

As a PCIe Design Engineer, you will architect and implement SoC-level RTL for our next-generation data center accelerators. Beyond designing high-performance PCIe subsystems, you will build the foundational SoC infrastructure—including clocking, reset, error handling, and chip management—that powers our silicon. This highly cross-functional role offers a "big picture" view of the product lifecycle from concept to production, requiring close collaboration with software and hardware teams to deliver accelerators.

This position offers the opportunity to work on challenging technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience in ASIC design, including one project focused on PCIe logic.
• Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
• Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
• Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM.
• Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.

Nice To Haves

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 8 years of ASIC design experience, including 3 years in PCIe (Gen4/5/6) controller or protocol logic.
• Knowledge of ASIC flow (DFT, synthesis, PnR), SerDes, and scripting (Python, Tcl, or Perl).
• Advanced RTL design skills mastering multi-clock domains, timing closure, datapath optimization, and hardware/firmware partitioning.
• Expertise in PCIe architecture, including LTSSM, TLP/FLIT pipelines, flow control, ordering rules, and performance tuning.
• Proven cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up.

Responsibilities

• Lead the PCIe microarchitecture and RTL development, ensuring high-performance designs that strictly adhere to PPA targets, coding standards, and quality guidelines.
• Manage the full RTL lifecycle, including documentation and coding, while ensuring the design is sign-off ready for Lint, CDC, and synthesis.
• Partner with system architects to integrate the PCIe subsystem, ensuring it meets chip-level bandwidth, latency, and power consumption goals.
• Coordinate with Verification and Physical Design teams to develop test plans, leverage PCIe VIP, and achieve successful timing closure.
• Resolve complex protocol issues and lead post-silicon bring-up to ensure link integrity and subsystem performance.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level