Architect DSP

Marvell Technology • Santa Clara, CA

2d

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Group Description Marvell’s Architecture team leads the industry in wireline Ethernet communication technologies, delivering solutions for applications ranging from hyperscale data center interconnects to industrial PHYs. Their portfolio spans speeds up to 1.6 Tb/s and supports diverse media types, including optical fibers, high-speed coaxial cables, and shielded/unshielded twisted pair cables. The underlying core technologies that enable these products are state of the art of equalization techniques like Maximum likelihood sequence estimation, timing synchronization, cross talk and echo cancellation techniques, error control coding techniques such as LDPC, product and concatenated codes, combined with architectural and circuit innovations to enable low power high speed implementation of these complex algorithms. Come join Marvell to work on the DSP and architecture challenges that need to be solved to enable products and technologies that will determine the future direction for the entire industry. What You Can Expect Lead to design and simulate DSP architecture, define key capabilities, performance requirements and drive specifications for both analog and digital designers. Create DSP and FEC hardware block specifications appropriate for RTL implementation. Perform research activities in digital signal processing for Base-T, SerDes and optical channels Lead designers to ensure circuit architecture can be efficiently implemented. Lead to Develop/perform behavioral modeling of mixed-signal circuit designs for transceivers. Provide guidance on test plans for lab characterization once design comes back from fab. Lead in chip lab bring up.

Requirements

• Ph.D., or M.S. in Electrical Engineering, Computer Science or related fields and 12+ years of related design experience.
• Strong knowledge of communications theory and system design, and digital signal processing.
• Deep architectural understanding of: High-speed interconnects and Ethernet protocols High Speed SerDes and Ethernet PHY architecture
• Proven hands-on experience with performance modeling, simulation, and architectural trade-off analysis.
• Proficiency in C/C++, Python, and modeling environments.
• Experience in high-speed DSP, especially FFE/DFE, Clock and Data Recovery (CDR) or FEC (RS, soft decoding, Viterbi algorithm)
• Strong conceptual thinking and architectural innovation capabilities.
• Collaborative leadership style; ability to work across silicon, systems, software, and customer engineering teams.
• Exceptional communication skills; able to convey complex architectural concepts to technical and executive audiences.
• Demonstrated experience mentoring and influencing engineering talent and product direction.

Nice To Haves

• Experience with ADC-based wireline transceivers and/or coherent DSP architectures is a plus.

Responsibilities

• Lead to design and simulate DSP architecture, define key capabilities, performance requirements and drive specifications for both analog and digital designers.
• Create DSP and FEC hardware block specifications appropriate for RTL implementation.
• Perform research activities in digital signal processing for Base-T, SerDes and optical channels
• Lead designers to ensure circuit architecture can be efficiently implemented.
• Lead to Develop/perform behavioral modeling of mixed-signal circuit designs for transceivers.
• Provide guidance on test plans for lab characterization once design comes back from fab.
• Lead in chip lab bring up.

Benefits

• employee stock purchase plan with a 2-year look back
• family support programs to help balance work and home life
• robust mental health resources to prioritize emotional well-being
• recognition and service awards to celebrate contributions and milestones

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: Ph.D. or professional degree